參數(shù)資料
型號(hào)： IS42S16400-10TI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 4M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝： 0.400 INCH, TSOP2-54
文件頁(yè)數(shù)： 13/54頁(yè)
文件大?。?/td> 580K
代理商： IS42S16400-10TI
IS42S16400
ISSI
Integrated Silicon Solution, Inc.
—
1-800-379-4774
TARGET SPECIFICATION
Rev. C
05/04/01
13
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6
-7
-10
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max
Units
t
CK3
t
CK2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
6
8
—
—
7
10
—
—
10
10
—
—
ns
ns
t
AC3
t
AC2
Access Time From CLK
(4)
CAS
Latency = 3
CAS
Latency = 2
—
—
5.5
6
—
—
6
6
—
—
7
9
ns
ns
t
CHI
CLK HIGH Level Width
2
—
2.5
—
3.5
—
ns
t
CL
CLK LOW Level Width
2
—
2.5
—
3.5
—
ns
t
OH3
t
OH2
Output Data Hold Time
CAS
Latency = 3
CAS
Latency = 2
2.5
2.5
—
—
2.5
2.5
—
—
2.5
2.5
—
—
ns
ns
t
LZ
Output LOW Impedance Time
0
—
0
—
0
—
ns
t
HZ3
t
HZ2
Output HIGH Impedance Time
(5)
CAS
Latency = 3
—
—
5.5
6
—
—
6
6
—
—
7
9
ns
ns
CAS
Latency = 2
t
DS
Input Data Setup Time
1.5
—
1.5
—
2.0
—
ns
t
DH
Input Data Hold Time
0.8
—
0.8
—
1
—
ns
t
AS
Address Setup Time
1.5
—
1.5
—
2.0
—
ns
t
AH
Address Hold Time
0.8
—
0.8
—
1
—
ns
t
CKS
CKE Setup Time
1.5
—
1.5
—
2.0
—
ns
t
CKH
CKE Hold Time
0.8
—
0.8
—
1
—
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+3
—
1CLK+3
—
1CLK+3
—
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1.5
—
1.5
—
2.0
—
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
0.8
—
0.8
—
1
—
ns
t
RC
Command Period (REF to REF / ACT to ACT)
60
—
63
—
70
—
ns
t
RAS
Command Period (ACT to PRE)
35
120,000
37
120,000
44
120,000
ns
t
RP
Command Period (PRE to ACT)
15
—
15
—
18
—
ns
t
RCD
Active Command To Read / Write Command Delay Time
15
—
15
—
18
—
ns
t
RRD
Command Period (ACT [0] to ACT[1])
14
—
14
—
15
—
ns
t
DPL3
Input Data To Precharge
Command Delay time
CAS
Latency = 3
2CLK
—
2CLK
—
2CLK
—
ns
t
DPL2
CAS
Latency = 2
2CLK
—
2CLK
—
2CLK
—
ns
t
DAL3
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
CAS
Latency = 3
2CLK+t
RP
—
2CLK+t
RP
—
2CLK+t
RP
—
ns
t
DAL2
CAS
Latency = 2
2CLK+t
RP
—
2CLK+t
RP
—
2CLK+t
RP
—
ns
t
T
Transition Time
1
10
1
10
1
10
ns
t
REF
Notes:
1. When power is first applied, memory operation should be started 100 μs after Vcc and Vcc
Q
reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.)
when the output is in the high impedance state.
Refresh Cycle Time (4096)
—
64
—
64
—
64
ms
相關(guān)PDF資料
PDF描述
IS42S16400-6T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S16400-6T 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16400-7T 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16400-7TI 制造商:Integrated Silicon Solution Inc 功能描述:
IS42S16400A 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16400A-7T 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II 制造商:Integrated Silicon Solution Inc 功能描述:SDRAM, 4M x 16, 54 Pin, Plastic, TSOP
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