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參數(shù)資料
| 型號： | IS41LV16400 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 4M x 16 DRAM With EDO Page Mode(3.3V,4M x 16 帶擴展數(shù)據(jù)輸出頁模式動態(tài)RAM) |
| 中文描述： | 4米× 16的DRAM與江戶頁面模式（3.3伏，4米× 16帶擴展數(shù)據(jù)輸出頁模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/19頁 |
| 文件大小： | 141K |
| 代理商： | IS41LV16400 |
IS41LV16400
ISSI
6
Integrated Silicon Solution, Inc.
—
1-800-379-4774
Rev. A
11/18/99
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
I
IL
Parameter
Input Leakage Current
Test Condition
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
I
OH
=
–
2.0 mA
I
OL
= 2.0 mA
RAS
,
LCAS
,
UCAS
≥
V
IH
Speed
Min.
–
5
Max.
5
Unit
μA
I
IO
Output Leakage Current
–
5
5
μA
V
OH
V
OL
I
CC
1
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
2.4
—
—
—
—
—
—
—
—
0.4
1
2
2
0.5
160
145
V
V
Commerical
Extended
Industrial
mA
mA
mA
mA
mA
I
CC
2
I
CC
3
Standby Current: CMOS
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
Refresh Current:
RAS
-Only
(2,3)
Average Power Supply Current
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS
,
LCAS
,
UCAS
≥
V
CC
–
0.2V
RAS
,
LCAS
,
UCAS
,
Address Cycling, t
RC
= t
RC
(min.)
-50
-60
I
CC
4
RAS
= V
IL
,
LCAS
,
UCAS
,
Cycling t
PC
= t
PC
(min.)
-50
-60
—
—
90
80
mA
I
CC
5
RAS
Cycling,
LCAS
,
UCAS
≥
V
IH
t
RC
= t
RC
(min.)
-50
-60
—
—
160
145
mA
I
CC
6
RAS
,
LCAS
,
UCAS
Cycling
t
RC
= t
RC
(min.)
-50
-60
—
—
160
145
mA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
319
50 pF
Including
jig and
scope
353
OUTPUT
3.3V
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF
Input timing reference levels: V
IH
= 2.0V, V
IL
= 0.8V
Output timing reference levels: V
OH
= 2.0V, V
OL
= 0.8V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS41LV16400-50T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Mx16 (64-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16400-50TE | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Mx16 (64-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16400-50TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Mx16 (64-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16400-60T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Mx16 (64-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16400-60TE | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Mx16 (64-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
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