參數(shù)資料
型號(hào)： IS41C16256-35K
英文描述： 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
中文描述： 256K × 16（4兆位）的動(dòng)態(tài)與江戶頁(yè)面模式內(nèi)存
文件頁(yè)數(shù)： 4/20頁(yè)
文件大小： 215K
代理商： IS41C16256-35K
IS41C16256
IS41LV16256
4
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
Functional Description
The IS41C16256 and IS41LV16256 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered 9 bits (A0-A8) at a time. The row address is latched
by the Row Address Strobe (
RAS
). The column address
is latched by the Column Address Strobe (
CAS
).
RAS
is
used to latch the first nine bits and
CAS
is used the latter
nine bits.
The IS41C16256 and IS41LV16256 has two
CAS
controls,
LCAS
and
UCAS
. The
LCAS
and
UCAS
inputs internally
generates a
CAS
signal functioning in an identical man-
ner to the single
CAS
input on the other 256K x 16
DRAMs. The key difference is that each
CAS
controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS
).
LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8 through I/O15.
The IS41C16256 and IS41LV16256
CAS
function is
determined by the first
CAS
(
LCAS
or
UCAS
) transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16256 both BYTE READ and
BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE
, whichever
occurs first.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS
-only cycle refreshes the
addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the
CAS
cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the V
CC
supply, an initial pause of
200 μs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
相關(guān)PDF資料
PDF描述
IS41C16256-35KI 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-35T 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-35TI 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-50K 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-50KI 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS41C16256-35KI 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C1625635T 制造商:ISSI 功能描述:*
IS41C16256-35T 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-35TI 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-40K 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM
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