參數(shù)資料
型號(hào): IRU3138
廠商: International Rectifier
英文描述: SYNCHRONOUS PWM CONTROLLER FOR TERMINATION POWER SUPPLY APPLICATIONS
中文描述: 同步PWM控制器終止電源應(yīng)用
文件頁(yè)數(shù): 9/18頁(yè)
文件大?。?/td> 281K
代理商: IRU3138
IRU3138
9
Rev. 1.0
01/29/04
www.irf.com
Choose IRLR3715Z for control MOSFET and IRFR3711Z
for synchronous MOSFET. These devices provide low
on-resistance in a D-Pak.
The MOSFETs have the following data:
The total conduction losses will be:
P
CON(TOTAL)
= P
CON(UPPER)
+ P
CON(LOWER)
P
CON(TOTAL)
= 1.77W
The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. The
control MOSFET contributes to the majority of the switch-
ing losses in synchronous Buck converter. The synchro-
nous MOSFET turns on under zero voltage conditions,
therefore, the turn on losses for synchronous MOSFET
can be neglected. With a linear approximation, the total
switching loss can be expressed as:
V
2
T
The switching time waveform is shown in Figure 7.
Figure 7 - Switching time waveforms.
From IRFR3711Z data sheet we obtain:
These values are taken under a certain condition test.
For more details please refer to the IRFR3711Z datasheet.
By using equation (12), we can calculate the total switch-
ing losses.
P
SW(TOTAL)
= 336mW
Feedback Compensation
The IRU3138 is a voltage mode controller; the control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensa-
tion circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 45
8
).
The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180
8
(see Figure 8). The Reso-
nant frequency of the LC filter is expressed as follows:
1
2
π×
L
O
×
C
O
Figure 9 shows gain and phase of the LC filter. Since we
already have 180
8
phase shift just from the output filter,
the system risks being unstable.
Figure 8 - Gain and phase of LC filter.
Where:
V
DS(OFF)
= Drain to Source Voltage at off time
t
r
= Rise Time
t
f
= Fall Time
T = Switching Period
I
LOAD
= Load Current
P
SW
=
I
LOAD
---(12)
×
t
r
+
t
f
×
IRFR3711Z
t
r
= 13ns
t
f
= 15ns
F
LC
= ---(13)
V
DS
90%
V
GS
10%
t
d
(ON)
t
d
(OFF)
t
r
t
f
Gain
F
LC
0dB
Phase
0
8
F
LC
-180
8
Frequency
Frequency
-40dB/decade
IRFL3715Z
V
DSS
= 20V
R
DS(ON)
= 11m
IRFR3711Z
V
DSS
= 20V
R
DS(ON)
= 5.7m
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