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參數(shù)資料
| 型號： | IRU3072C |
| 廠商： | International Rectifier |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | 20-PIN SYNCHRONOUS PWM CONTROLLER/ 3 LDO CONTROLLER |
| 中文描述： | 20引腳同步PWM控制器/ 3 LDO控制器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | IRU3072C |
8
Rev. 1.0
3/25/04
IRU3072
www.irf.com
Figure 6 - Power sequence.
If there are three input voltage sources available, such
as 3.3V, 5V and 12V, the possible connections to en-
sure proper operation are shown in the following table.
Table: Possible combination of input voltage source
connections to ensure proper start-up operation.
(CP refers to Charge Pump)
There are many possible combinations of input voltage
source connections and the table above lists only a few
of them. Most importantly for a proper power sequence,
the soft-start capacitor has to be charged up after all the
input voltage sources are established.
Soft-Start
One of the useful features of IRU3072 is that it allows
different start-up times for PWM output and LDO output
by programming two separate soft-start capacitors. Fig-
ure 7 just shows the soft-start for PWM section.
64
μ
A
×
25K
= 1.6V
Option
1
2
3
4
more
Vcc
5V
5V
12V
12V
V
BUS
5V
12V
12V
5V
Vc
12V
CP
CP
12V
VccLDO
12V
12V
12V
12V
LDO Input
3.3V
3.3V
3.3V
3.3V
The soft-start operation can ensure the output voltage
ramps up to the regulated voltage without surge of the
current. The IRU3072 also has an output feedback UVLO
block, which will turn off both high side and low side
MOSFET driver when the voltage at pin Fb1,Fb2,Fb3 or
Fb4 is below 0.4V. The feedback UVLO is used to pro-
tect the system when the output is in short circuit. How-
ever, during the power on of the buck converter, the out-
put of buck converter starts from zero and the voltage at
pin Fb1 will be below 0.4V. The feedback UVLO should
be disabled when soft-start capacitor voltage ramps up
and down. This is achieved by injecting a current into
the Fb1 pin (also Fb2, Fb3 and Fb4) during the soft-start
and the magnitude of this current is inversely propor-
tional to the voltage at soft-start pin (SS or SSLDO). The
diagram is shown in Figure 7 and operation waveforms
are shown in Figure 8. The operation principle is as
follows:
Initially, the buck converter’s output voltage and the volt-
age at pin Fb1 are both zero. The voltage at soft-start pin
“SS” is almost zero and about 64
μ
A current will inject to
the pin of Fb1 through a 25K
internal resistor. The
voltage at the negative input of Error Amplifier and the
positive input of the feedback UVLO comparator is ap-
proximately:
Figure 7 - IRU3072 soft-start diagram.
20uA
64uA
Max
POR
Error Amp
64uA
×
25K=1.6V
When SS=0
POR
0.4V
Feeback
UVLO Comp
SS1
Fb1
Comp
25K
0.8V
25K
HDrv
LDrv
3V
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