參數(shù)資料
型號: IRS2500SPBF
廠商: International Rectifier
文件頁數(shù): 15/22頁
文件大小: 419K
描述: IC PFC
產(chǎn)品培訓模塊: IRS2500 PFC Control IC Overview
標準包裝: 95
系列: *
 
IRS2500S
 
www.irf.com
?2012 International Rectifier
15
 
PCB Layout Guidelines
 
For correct operation of the IRS2500, the PCB
should be designed to avoid noise coupling to the
control inputs and ground loops. By following the
recommendations listed here potential issues will be
avoided:
 
1. The circuit signal and power grounds should be
joined together at one point only. The signal ground
should be a star point located close to the COM pin
of the IRS2500.
 
2. The point at which the signal ground is connected
to the power ground is recommended to be at the
current sense resistor (ROC) ground.
 
3. A 0.1糉 noise decoupling capacitor should be
located between the VCC and COM pins of the
IRS2500 located as close to the IC as possible.
 
4. All traces to the VBUS input should be as short as
possible. This means that resistors and capacitors
that are connected to this input should be located as
close to the IRS2500 as possible. The voltage
feedback divider resistor connected to COM should
be connected to a signal ground close to the COM
pin.
 
5. Traces carrying high voltage switching signals
such as those connected to the MOSFET drain or
gate drive signals should not be located close to
traces connected directly to the VBUS input.
 
6. The divider network resistor (RDC) and filter
capacitor (CDC) connected to the VDC input of the
IRS2500 should be located as closely to the IC as
possible with the grounded end connected to the
circuit signal ground.
 
7. The compensation capacitor CCOMP should be
located close to the IRS2500 with short traces
leading to the VBUS and COMP pins.
 
8. The over current detection filter resistor (ROC)
and capacitor (COC) should be located as close to
the IRS2500 as possible with COC connected to the
circuit signal ground.
 
9. The zero crossing detection resistor should be
located close to the IRS2500 if possible to prevent
possible noise appearing at this input.
 
 
 
 
 
 
 
 
Figure 14: Layout Example 
 
Figure 14 shows a layout where the IRS2500 is
located on the bottom side of the PCB. The bottom
side traces are shown in red and the top side traces
in pale blue. The circuit power ground can be seen
at the C2 GND node with the signal ground star
point is located at the junction between RPFC6 and
CPFC4 to the left of the IRS2500 (IC1). (Note that
the component designators in this example are
different from those used in the datasheet
schematics)
The traces from IC1 pin 6, RPFC3 and CPFC1 (the
VDC divider low side) all run directly to the star
point without crossing any other grounds. The
signal ground is connected to the power ground at
the current sense resistor. A large trace can be
seen running from the star point off the left to where
the MOSFET is situated (not shown). This is the
single point where the signal and power grounds
are connected. The VCC supply decoupling
capacitor shown in this example is CPFC4, which is
located very close to the IRS2500 and grounded
directly to the signal ground star point.
Traces leading to pin 1 (VBUS) are all short and
components connected to pin 1 (RPFC5, RPFC6
and RPFC7) are all located close to IC1. There are
no traces connected to high voltage switching
nodes located anywhere close to pin 1.
The board layout shown in figure 14 complies with
all of the guidelines stated enabling optimum
operation of the IRS2500.
 
 
 
 
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