參數(shù)資料
型號(hào)： IR3Y38M
廠商： Sharp Corporation
英文描述： PLIERS, COMBINATION REDLINE 180MMPLIERS, COMBINATION REDLINE 180MM; Jaw type:Combination; Length:180mm; Handle type:High grip; Capacity, cutting:1.6mm; Capacity, cutting hard wire:1.6mm; Joint Construction:lap; Length, jaw:40mm;
中文描述： CCD信號(hào)處理
文件頁(yè)數(shù)： 8/21頁(yè)
文件大?。?/td> 152K
代理商： IR3Y38M
IR3Y38M
8
FUNCTIONAL DESCRIPTION
CDS Circuit
The clamp circuit clamps the feed-through level of
the CCD signal with the pulse. Then the fl/H
1
circuit samples the signal period of the one with the
fl/H
1
pulse and holds on. Thus the video signal is
obtained. But this signal has a level drop caused by
the reset pulse of the CCD signal, and for removing
it, the fl/H
2
circuit samples this signal again with the
fl/H
2
pulse.
For reducing the effect of the sampling pulse or
other noise sources, the CDS circuit is formed with
a differential structure.
Bias Error Amplifier Circuit
For stabilizing the bias level of the CDS circuit and
reducing the offset of the AGC circuit, the bias error
amplifier acts with the pulse during the OPB
period.
AGC Amplifier Circuit
The AGC amplifier amplifies the video signal
obtained by the CDS circuit. The gain of the AGC
is controlled by the value of the AGCGAIN serial
register. And the maximum gain of the AGC is
controlled by the value of the GAINSEL serial
register.
OPB Clamp Circuit
For clamping the level of the amplified signal to the
black level, the OPB clamp circuit acts with the
pulse during the OPB period.
Blanking Circuit
The output signal is fixed to the blanking level with
the pulse. The blanking level is the sum of the
black level and the offset value decided by the
value of the OFFSET serial register.
A/D Converter Circuit
The fl/H
3
circuit samples the amplified signal with
the fl/H
3
pulse and the A/D converter converts the
sampled signal to 10-bit straight binary digital data.
The clamp circuit placed in front of the A/D
converter clamps the signal level beside the lower
limit of the convertible input range with the
pulse. The clamped level is controllable by the
voltage of the ADOFS pin.
The A/D conversion is executed at the rising edge
of the ADCK clock, and the data is output at the
falling edge.
The high level voltage of the outputs is controlled
by the voltage of the V
LOGIC
pin.
Standby Function
By making the ‰ pin low, all actions of this IC
stop and power consumption is decreased.
The outputs of the A/D converter (DO
0
to DO
9
) turn
to high impedance when on standby.
PIN NO.
PIN NAME VOLTAGE
EQUIVALENT CIRCUIT
DESCRIPTION
48
V
LOGIC
3.3 V
ADC output voltage setting pin. The
high level voltage of the DO
0
to
DO
9
pins is set to V
LOGIC
– 0.2 V.
It is recommended to connect to the
power supply of the following logic
ICs.
25 μ
V
CC5
200
GND
5
48
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