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參數(shù)資料
| 型號(hào)： | IR3Y38 |
| 廠商： | Sharp Corporation |
| 英文描述： | CCD Signal Process & Digital Interface IC |
| 中文描述： | CCD信號(hào)處理 |
| 文件頁(yè)數(shù)： | 18/21頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | IR3Y38 |
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IR3Y38M
18
A/D Converter Circuit
(Unless otherwise specified, T
A
= +25 C, V
CC1
= V
CC2
= V
CC3
= V
CC4 =
V
CC5 =
V
CC6 =
5.0 V, V
LOGIC
= 3.3 V,
ADCK = 18 MHz square wave, = 0 V, ˙ = 0 V, ‰ = 3.3 V, = 3.3 V, fl/H
1
= 0 V, fl/H
2
= 0 V,
fl/H
3
= 0 V, = 3.3 V, = 3.3 V, SW42 = OFF, SW43 = (b), = 3.3 V)
PARAMETER
SYMBOL
CONDITIONS
SW43 = (a)
= 0 V
ADCIN = GND
4
Read the output value of DO
0
to DO
9
.
SW42 = ON, V
42
= 5.0 V, = 0 V,
ADCIN = GND
4
Read the output value of DO
0
to DO
9
.
SW42 = ON, V
42
= 1.6 V, = 0 V,
ADCIN = GND
4
Read the output value of DO
0
to DO
9
.
TYP.
Clamp value
D
CLP
61
56
MIN.
–
UNIT
66
MAX.
41
–
31
36
D
CLPN
Clamp value
adjustment limit (1)
Differential linearity
error
DLE
ADCIN = SG4
Read the output value of DO
0
to DO
9
at about
10
6
times and make it a histogram. Normalize
the histogram and obtain the DLE.
Integrate the histogram and obtain the ILE.
ADCIN = SG4, C
L
= 20 pF
Measure the delay time from the falling edge
(50%) of the ADCK to the rising edge (50%)
of the DO
0
to DO
9.
ADCIN = SG4, C
L
= 20 pF
Measure the delay time from the falling edge
(50%) of the ADCK to the falling edge (50%)
of the DO
0
to DO
9.
±0.5
–
LSB
±0.9
Clamp value
adjustment limit (2)
D
CLPX
86
81
–
91
Propagation delay
(L
/
H)
t
DLH
26
15
ns
38
ILE
Integral linearity error
±7
LSB
–
±3
25
ns
10
17
ADCIN = SG4, C
L
= 20 pF
Measure the fall time (90%
/
10%) of the
DO
0
to DO
9.
t
WHL
Output fall time
25
ns
10
17
ADCIN = SG4, C
L
= 20 pF
Measure the rise time (10%
/
90%) of the
DO
0
to DO
9.
t
WLH
Output rise time
38
ns
15
26
t
DHL
Propagation delay
(H
/
L)
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相關(guān)代理商/技術(shù)參數(shù) |
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