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參數(shù)資料
| 型號： | IR3623MPBF |
| 廠商： | International Rectifier |
| 英文描述： | HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING |
| 中文描述： | 高頻2相，單或雙輸出同步降壓控制器，輸出跟蹤和排序 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 523K |
| 代理商： | IR3623MPBF |
IR3623MPbF
www.irf.com
Compensation
(slave channel)
The
slave
transconductance
configuration the main goal for the slave channel
feedback loop is to control the inductor current to
match the master channel inductor current as
well provides highest bandwidth and adequate
phase margin for overall stability. The following
analysis is valid for both using external current
sense resistors and using DCR of inductor.
The transfer function of power stage is
expressed by:
V
V
2
e
*
for
Current
Loop
error
amplifier
amplifier,
is
in
differential
2-phase
Where:
V
in
=Input voltage
L
2
=Output inductor
V
osc
=Oscillator Peak Voltage
As shown the G(s) is a function of inductor
current. The transfer function for compensation
network is given by equation (23), when using a
series RC circuit as shown in figure21.
The loop gain function is:
22
)
22
(
V
sL
s
I
s
G
osc
in
2
L
)
(
)
(
=
=
L
2
L
1
C
2
R
2
R
S2
R
S1
Ve
I
L2
I
L1
Fb2
E/A2
Comp2
Vp2
)
23
(
sC
R
sC
1
R
R
g
R
s
V
s
D
2
2
2
2
s
1
s
m
2
s
e
=
=
*
*
)
(
)
(
[
]
2
s
R
s
D
s
G
s
H
*
(
*
(
)
(
=
1
=
osc
2
in
2
2
2
2
s
1
s
m
2
s
V
sL
V
sC
C
sR
R
R
g
R
s
H
*
*
*
*
*
)
(
Select a zero frequency for current loop (F
o2
)
1.25 times larger than zero cross frequency for
voltage loop (F
o1
).
From (24), R2 can be expressed as:
V
in
=13.2V
V
osc
=1.25V
g
m
=2800umoh
L
2
=0.34uH
R
s1
=DCR=1.1mOhm
F
o2
=125kHz
This results to : R
2
=8.2K
The power stage of current loop has a dominant
pole (Fp) at frequency expressed by:
Where R
eq
is the total resistance of the power
stage which includes the R
ds(on)
of MOSFET
switches, the DCR of inductor and shunt
resistance (if it used).
R
eq
=9.4mOhm
Set the zero of compensator at 10 times the
dominant pole frequency F
P
, the compensator
capacitor, C2 can be expressed as:
C
2
=0.47nF
All design should be tested for stability to verify
the calculated values.
1
O
2
O
F
25
.
1
F
*
%
)
24
(
1
V
L
F
2
V
R
R
g
F
H
osc
2
2
O
in
*
2
1
s
m
2
O
=
=
*
*
*
*
*
)
(
π
)
25
(
V
V
L
F
2
R
g
1
*
R
in
osc
2
2
O
1
s
m
2
*
*
*
*
π
=
L
2
R
π
F
2
eq
*
P
=
s
L
on
ds
eq
R
R
R
R
+
+
=
)
(
z
2
2
P
1
z
F
R
2
C
F
10
F
*
*
*
π
=
=
Fig. 21: The Compensation network for current loop
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