參數(shù)資料
型號(hào)： IR3093M
廠商： International Rectifier
英文描述： 3 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
中文描述： 3相皓龍，速龍，或控制IC的VR10.X
文件頁(yè)數(shù)： 22/39頁(yè)
文件大小： 693K
代理商： IR3093M
IR3093
Page 22 of 39
07/15/04
A delay is included if an over-current condition occurs after a successful soft-start sequence. This is required since
over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an over-
current fault occurs during normal operation, the Over Current Comparator will initiate the discharge of the
capacitor at SS/DEL but will not set the fault latch immediately. If the over-current condition persists long enough
for the SS/DEL capacitor to discharge below the 250mV offset of the delay comparator, the Fault latch will be set
pulling the Error Amplifier’s output low inhibiting switching in the phase ICs and de-asserting the PWRGD signal.
See Soft Start, Over-Current Fault Delay, and Hiccup Mode. The hiccup mode duty cycle of over current protection
is determined by the ratio of the charge to discharge current and is fixed at 9.1% for the ratio of 10 to 1.
The inductor DC resistance R
L
is utilized to sense the inductor current. The current limit threshold is set by a
resistor R
OCSET
connected between the OCSET and VDAC pins, as shown in Fig1. I
LIMIT
is
the required over
current limit. I
OCSET,
the bias current of OCSET pin, is set by R
ROSC
and is determined by the curve in this data
sheet. OCP need to satisfy the high temperature condition. R
L_MAX
and R
L_ROOM
are the inductor DCR at
maximum temperature T
L_MAX
and room temperature T_
ROOM
respectively, the maximum inductor DCR can be
calculated from Equation (8)
(
10
*
3850
1
_
_
_
MAX
L
ROOM
L
MAX
L
T
R
R
The current sense amplifier gain of IR3093 decreases with temperature at the rate of1400 PPM, which
compensates part of the inductor DCR increase. The minimum current sense amplifier gain at the maximum IC
temperature T
IC_MAX
is calculated from Equation (9).
(
10
*
1400
1
_
_
IC
ROOM
CS
MIN
CS
T
G
G
R
OCSET
can be calculated by the following equation (10), where
¨
I is the ripple current in each output inductor.
I
I
R
]
)
2
3
Vo
Vin
Vo
I
'
(11)
)]
6
ROOM
T
(8)
)]
_
6
ROOM
T
MAX
(9)
OCSET
MIN
CS
MAX
L
LIMIT
OCSET
I
G
R
/
[(
_
_
'
(10)
fsw
Vin
L
)
(
Adaptive Voltage Positioning
Adaptive voltage positioning is needed to reduce output voltage deviations during load transients and power
dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in
Figure 8. Resistor R
FB
is connected between the Error Amplifier’s inverting input pin FB and the converter’s output
voltage. An internal current source whose value is programmed by the same external resistor that programs the
oscillator frequency, R
ROSC
, pumps current out of the FB pin. The FB bias current develops a positioning voltage
drop across R
FB
which forces the converter’s output voltage lower to V(VDAC)-I(FB)* R
FB
to maintain a balance at
the Error Amplifier inputs. R
FB
is selected to program the desired amount of fixed offset voltage below the DAC
voltage.
The voltage at the VDRP pin is an average of three phase Current Sense Amplifiers and represents the sum of the
VDAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin
through the resistor. The Error Amplifier forces the voltage on the FB pin to equal VDAC through the power supply
loop therefore the current through RDRP is equal to (VDRP-VDAC) / R
DRP.
As the load current increases, the
VDRP voltage increases accordingly which results in an increase R
FB
current, further positioning the output
regulated voltage lower thus making the output voltage reduction proportional to an increase in load current. The
droop impedance or output impedance of the converter can thus be programmed by the resistor R
DRP.
The offset
and slope of the converter output impedance are independent of the VDAC voltage.
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