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  • 參數(shù)資料
    型號(hào): IR21771S
    廠商: International Rectifier
    英文描述: Phase Current Sensor IC for AC motor control
    中文描述: 相電流傳感器IC交流電機(jī)控制
    文件頁(yè)數(shù): 9/16頁(yè)
    文件大小: 441K
    代理商: IR21771S
    IR22771S/IR21771S
    (PbF)
    A residual offset can be read in PO duty cycle
    according
    to
    V
    POs
    (see
    characteristics).
    According to Figure 8, it can be assumed that odd
    cycles are represented by SYNC at high level
    (channel 1) and even cycles represented by SYNC
    at low level (channel 2).
    The two channels are independent in order to
    provide the correct duty cycle value of PO even for
    non-50% duty cycle of SYNC signal. Small variation
    of SYNC duty cycle are then allowed and
    automatically corrected when calculating the duty
    cycle using
    Eq. 1
    .
    However, channel 1 and channel 2 can have a
    difference in offset value which is specified in
    V
    POS
    (see Static electrical characteristics).
    To implement a correct offset compensation of PO
    duty cycle, each channel must be compensated
    separately.
    1.3 Over Current output (OC)
    OC output is an open drain pin (active low).
    A simplified block diagram of the over current circuit
    is shown in the Figure 9.
    Over current is detected when |
    V
    in
    |=|V
    inp
    -V
    inm
    |>V
    OCth
    .
    If an event of over current lasts longer than t
    dOCon
    ,
    OC pin is forced to V
    SS
    and remains latched until
    PO is externally forced low for at least t
    OCoff
    (see
    timing on Figure 4). During an over current event
    (OC is low), PO is off (pulled-up by external
    resistor).
    If OC is reset by PO and over current is still active,
    OC pin will be forced low again by the next edge of
    SYNC signal.
    To reset OC state PO must be forced to V
    SS
    for at
    least T
    OCoff
    .
    Auto reset function
    The auto reset function consists in clearing
    automatically the OC fault.
    To enable the auto reset function, simply short
    circuit the OC pin with the PO pin.
    9
    www.irf.com
    1
    1.1 SYNC input
    Sync input clocks the whole device. In order to
    make the device work properly it must be
    synchronous with the triangular PWM carrier as
    shown in Figure 8.
    SYNC pin is internally pulled-down (10 k
    ) to V
    SS
    .
    1.2 PWM Output (PO)
    PWM output is an open collector output (active low).
    It must be pulled-up to proper supply with an
    external resistor (suggested value between 500
    and 10k
    ).
    DEVICE DESCRIPTION
    Figure 7:
    PO rising and falling slopes
    PO pull-up resistor determines the rising slope of
    the PO output and the lower value of PO as shown
    in Figure 7, where
    RC
    =
    τ
    capacitance and R is the pull-up resistance.
    R
    Supply
    V
    +
    where
    R
    on
    is the internal open collector resistance
    and
    R
    pull-up
    is the external pull-up resistance.
    PO duty cycle is defined for active low logic by the
    following formula:
    T
    D
    _
    PO duty cycle (
    D
    n
    ) swings between 10% and 30%.
    Zero input voltage corresponds to 20% duty cycle.
    , C is the total PO pin
    up
    pull
    on
    on
    low
    R
    R
    =
    Eq. 1
    n
    cycle
    T
    n
    cycle
    off
    n
    1
    _
    _
    +
    =
    Static
    electrical
    τ
    V
    low
    Supply
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