參數(shù)資料
型號： IR2167S
廠商： International Rectifier
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： PFC Ballast Control. Thermal Overload Protection. Brown Out Protection. Programmable Preheat and Frequency. Programmable Deadtime in a 20 Lead SOIC package
中文描述： PFC的鎮(zhèn)流器控制。熱過載保護(hù)。欠壓保護(hù)?？删幊填A(yù)熱和頻率?？删幊趟绤^(qū)時間在20引腳SOIC封裝
文件頁數(shù)： 21/30頁
文件大小： 937K
代理商： IR2167S
IR2167(
S
)
www.irf.com
21
Lamp Protection & Automatic Restart Circuitry Operation
from oscillator
section
+V
BUS
from lower
lamp cathode
R
CS
R3
R4
R5
R2
C1
R1
Q2
R
OC
C2
V
CC
OVER-
TEMP
DETECT
2
4.0V
5.1V
9.5V
3.0V
5.1V
1
1.0uA
7
CPH
DT
VDC
Q
T
R
Q
13
SD
14
0.2V
CS
Q
S
R
Q
Q
D
R
Q
CLK
Q
S
R
Q
UNDER-
VOLTAGE
DETECT
5.1V
8
50uA
7.6V
7.6V
7.6V
OC
3V
1V
FAULT
COUNTER
QUICK
RESTART
LOGIC
C
OC
2V
1meg
C4
from upper
lamp cathode
R7
R6
C3
Figure 12:
Lamp Protection & Automatic Restart circuitry block diagram with external component connection
Sensing the AC Line Voltage
The first of these protection pins senses the voltage on the
AC line by means of an external resistor divider (R1, R2 and
capacitor C1) and an internal comparator with hysterisis.
When power is first supplied to the IC at system startup,
three conditions are required before oscillation is initiated:
1.) the voltage on the VCC pin must exceed the rising
undervoltage lockout threshold (11.5V), 2.) the voltage at
the VDC pin must exceed 5.1V, and 3.) the voltage on the
SD pin must be below approximately 4.85V. If a low ac line
condition occurs during normal operation, or if power to the
ballast is shut off, the ac line will collapse prior to the VCC of
the chip (assuming theVCC is derived from a charge pump
off of the output of the half-bridge). In this case, the voltage
on the VDC pin will shut the oscillator off, thereby protecting
the power transistors from potentially hazardous hard switch-
ing. Approximately 2V of hysterisis has been designed into
the internal comparator sensing the VDC pin, in order to
account for variations in the ac line voltage under varying
load conditions. When the ac line recovers, the chip re-
starts from the beginning of the control sequence, as shown
in timing diagram (See Figure 13).
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