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參數(shù)資料
| 型號： | IR1110 |
| 廠商： | International Rectifier |
| 英文描述： | SOFT START CONTROLLER IC |
| 中文描述： | 軟起動控制器芯片 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大小： | 227K |
| 代理商： | IR1110 |
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IR1110
ADVANCE INFORMATION
www.irf.com
Operating Scenarios and Design Options
Power Supply Response Characteristics
The UV comparator responds to the amplitude of the V
DD
supply, to control the ramp clamp.
In order to correctly accomplish this function, the power supply should have the response
characteristics illustrated in Figure 11, and 1-phase shutdown must be enabled. A minimum rise
time of 100msec during initial power-up is required to provide sufficient delay time, before the
output of the UV comparator goes high, for V
PK
to become established before ramp-up commences.
During loss of line voltage, V
DD
should not hold up above 4.0V for more than 40msec, to
ensure timely clamping of the ramp via the UV comparator.
The snubber derived power supply in Figure 10 has the required rise time, however hold-
up time exceeds 40msec. Timely clamping of the ramp can instead be accomplished by the
external Loss of Line Shutdown circuit, described below.
If 1-phase shutdown is disabled, the rise time of VDD must be increased to about
200msec to control the ramp clamping function. In this case it may generally be better to control
the ramp clamp via the UVLO comparator, by increasing CUVLO to 0.22uF. The rise time of VDD
is no longer critical, and can have a minimum value of 1msec.
Loss of Line Shutdown circuits
The Loss of Line Shutdown circuit in Figure 12 clamps the ramp during line outage, via
the Undervoltage Lockout Comparator.
The Note (3) option of Figure 12 also eliminates dependence on a minimum power supply
rise time of 80msec. C
UVLO
is increased to 0.22uF, to provide sufficient delay during power-up, via
the UVLO Comparator. The rise time of the power supply is not now critical, and can have a
minimum value of 2.0msec.
A side effect of increasing C
UVLO
is to increase the shutdown time when one phase is lost.
With Pin 14 connected to V
SS
, this is corrected by Q1 being turned on during each 1-phase loss
pulse, which adds to the discharge current for C
UVLO
, via R1.
Low Line Shutdown circuit
The Low Line Shutdown circuit in Figure 12 clamps the ramp and removes the SCR firing
pulses if the line voltage falls to less than 85% of the minimum normal operating level. This circuit
may not be necessary for all applications, but its inclusion will provide added insurance of correct
operation during abnormal low line conditions.
Loss of one phase during three phase operation
The 1-Phase Shutdown circuit clamps the ramp and removes the SCR firing pulses if one
input phase is lost for more than about one cycle. When the missing phase returns, the ramp is
unclamped and the bus voltage ramps back to the set value.
If 1-Phase Shutdown is disabled, the IR1110 will continue to deliver DC bus voltage when
one input phase is lost. A potential problem arises, however, if the bus voltage is being regulated
significantly below the maximum value. If one phase is lost and the ramp remains unclamped for
more than one or two cycles, when the missing phase returns the bus voltage may transiently
jump to almost the maximum possible value, before it is regulated back to the set value. This can
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