- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360914 > IQX320-7PP391 User Programmable Special Function ASIC PDF資料下載
參數(shù)資料
| 型號： | IQX320-7PP391 |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 17/65頁 |
| 文件大小： | 620K |
| 代理商： | IQX320-7PP391 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
IQX Family Data Sheet
June 2000
Revision 5.0
17
device
die
has the Row Address of Binary (i) and Column
Address of Binary (j), or vice versa. Furthermore, when dealing
with the bondout devices IQX240B and IQX128B the I/O Port
numbers on the device
package
must first be mapped to the I/O
Port number on the device
die
to determne the Row and
Column Address of the
real
SRAM cell. Refer to Appendix A for
the tables and decision logic used to determne the location of
the real SRAM cell, and the mapping of I/O Port numbers on the
device package to I/O Port numbers on the device die.
The Control bus, {P/
S
=0, C[1:0]} specifies the type of connection
change, either make or break; the Row and Column Addresses
are the values corresponding to the two I/O Port numbers as
determned using the tables in Appendix A. P/
S
is set to 0 when
changing Switch Matrix connections using RapidConfigure.
As indicated in Table 4, when the control bit C1 is held low
during a make or break operation, the remaining SRAM cells
belonging to the word addressed by the Row Address are
automatically cleared. This feature can be used to speed up
connection changes as described below.
In one common crossbar application, the signal I/O Ports on the
device are divided into equal groups of inputs and outputs, and a
pin in the output group is required to be connected to any pin in
the input group. By judicious assignment of the I/O Ports to the
output group, one can ensure that for
every
output port, the
real
SRAM cells controlling the connection between that output port
and
all
ports in the input group fall on the word corresponding to
the output port number. With this assignment, when establishing
a new connection using RapidConfigure, any existing connection
to that output I/O Port is automatically broken (C1=0). Thus a
connection change, i.e., breaking an existing connection and
then making a new one, can be accomplished in one
RapidConfigure cycle. Tables in Appendix A provide information
on determning the word locations of real SRAM cells. Refer to I-
Cube’s application notes for further details of using
RapidConfigure.
Attempting to alter the contents of the SRAMcells responsible
for connections to the I/O Ports used for the RapidConfigure
Interface will result in unpredictable results.
Notes:
(1)
Binary (j) is the m-bit binary equivalent value of i. Right most bit is LSB. mequals Row/Column Address width. “i” and “j” refer to the I/O Port
number on the device die.
(2) “r” is the I/O Port number on the die corresponding the highest available signal I/O Port.
(3) Assumes the real SRAM cell controlling the connection has Row Address=Binary(j)
Operation
Control Bus
{P/S, C[1:0]}
010
Row Address
RA[m-1:0]
BINARY(i)
Column Address
CA[m-1:0]
BINARY(j)
Break the connection between I/O Ports i & j by writing a “0” to the SRAM cell location whose
Row Address is i and Column Address is j, [0
≤
i, j
≤
r]. Other SRAM cells are unchanged,
i.e., no other connections are affected.
(2,3)
Make the connection between I/O Ports i & j by writing a “1” to the SRAM cell location whose
Row Address is i and Column Address is j, [0
≤
i, j
≤
r]. Other SRAM cell are unchanged, i.e.,
no other connections are affected.
(2,3)
Break the connection between I/O Ports i & j by writing a “0” to the SRAM cell location whose
Row Address is i and Column Address is j, [0
≤
i, j
≤
r]. Clear all SRAM cells on row i; i.e.,
break all the connections controlled by the
real
SRAM cells belonging to row i.
(2,3)
Make the connection between I/O Ports i & j by writing a “1” to the SRAM cell location whose
Row Address is i and Column Address is j, [0
≤
i, j
≤
r]. Clear all SRAM cells on row i; i.e.,
break all the connections controlled by the
real
SRAM cells belonging to row i.
(2,3)
011
BINARY(i)
BINARY(j)
000
BINARY(i)
BINARY(j)
001
BINARY(i)
BINARY(j)
Table 4. Changing Switch Matrix Connections Using RapidConfigure
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IQX320-PB416 | User Programmable Special Function ASIC |
| IR00 | ASIC |
| IR01HD224-P2 | PERIPHERAL DRIVER|1 DRIVER|CMOS|SIP|9PIN|PLASTIC |
| IR01HD420 | PERIPHERAL DRIVER|1 DRIVER|CMOS|SIP|9PIN|PLASTIC |
| IR01HD420-P2 | PERIPHERAL DRIVER|1 DRIVER|CMOS|SIP|9PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IQXO-22C-24.0 | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-22C-32MHZ | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-22C-4.0 | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-22C-50.0 | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-331-100.0MHz | 制造商:IQD Frequency Products 功能描述:CRYSTAL OSCILLATOR 100.000000MHZ |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。