參數(shù)資料
型號(hào)： INTEL386 CXSA
廠商： Intel Corp.
英文描述： 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器)
中文描述： 5V的32位嵌入式微處理器完全靜態(tài)（5V的，32位完全靜態(tài)嵌入式微處理器）
文件頁(yè)數(shù)： 5/21頁(yè)
文件大?。?/td> 265K
代理商： INTEL386 CXSA
Intel386 CXSA EMBEDDED MICROPROCESSOR
5
2.0
PIN DESCRIPTIONS
Table 2 lists the Intel386 CXSA microprocessor pin descriptions. The following definitions are used in the pin
descriptions:
#
I
O
I/O Input and output signal.
P
Power pin.
G
Ground pin.
The named signal is active low.
Input signal.
Output signal.
Table 2. Pin Descriptions
Symbol
A20M#
(Note 1)
Type
Pin
45
Name and Function
Address 20 Mask
controls the A20 address signal. When
A20M# is low, the CPU masks off (forces low) the internal A20
physical address signal. This enables the CPU to run software
that was developed using the 8086 address “wraparound”
techniques. When A20M# is high, A20 is available on the
address bus. While the bus is floating, A20M# has no effect
on the A20 address signal. A20M# should be deasserted dur-
ing SMM if the SMM handler accesses more than 1 Mbyte of
memory.
Address Bus
outputs physical memory or port I/O addresses.
I
A25:1
(Note 2)
O
47–46, 80–79,
76–72, 70, 66-
64, 62–58,
56–51, 18
16
ADS#
O
Address Status
indicates that the processor is driving a valid
bus-cycle definition and address onto its pins (W/R#, D/C#,
M/IO#, BHE#, BLE#, and A25:1).
Byte High Enable
indicates that the processor is transferring
a high data byte.
Byte Low Enable
indicates that the processor is transferring
a low data byte.
Busy
indicates that the math coprocessor is busy.
CLK2
provides the fundamental timing for the device.
Data/Control
indicates whether the current bus cycle is a
data cycle (memory or I/O) or a control cycle (interrupt
acknowledge, halt, or code fetch). When D/C# is high, the bus
cycle is a data cycle; when D/C# is low, the bus cycle is a con-
trol cycle.
Data Bus
inputs data during memory read, I/O read, and
interrupt acknowledge cycles and outputs data during mem-
ory and I/O write cycles.
BHE#
O
19
BLE#
O
17
BUSY#
CLK2
D/C#
I
I
O
34
15
24
D15:0
I/O
81–83, 86–90,
92–96, 99–100,
1
NOTES:
1. This pin supports the additional features of the Intel386 CXSA microprocessor; it is not present on the Intel386 SXSA microprocessor.
2. The A25:24 pins support the additional features of the Intel386 CXSA microprocessor; they are not present on the Intel386 SXSA micro-
processor.
相關(guān)PDF資料
PDF描述
INTEL386 CXSB Low-Voltage, 32-Bit, Fully Static Embedded Microprocessor(低電壓32位完全靜態(tài)嵌入式微處理器)
intel386 DX 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
Intel386 EX Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
INTEL386 SXSA 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器)
intel386 SX 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTEL386SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR
INTEL387 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR
INTEL387DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR
INTEL387SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR
INTEL387TMDX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR
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