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參數(shù)資料
| 型號： | INA-12063-BLK |
| 英文描述： | 1.5 GHz Low Noise Self-Biased Transistor Amplifier |
| 中文描述： | 1.5 GHz的低噪聲自偏置晶體管放大器 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 351K |
| 代理商： | INA-12063-BLK |
6-131
A
1
C
C (50
)
B
A (
Γ
opt
*)
2
1
-2
B
0.5
0.5
0.2
-0.2
0.2
2
-0.5
-1
IRF
L1
C1
Figure 17. Input Impedance Match.
As shown in Figure 17, a shunt
capacitor of 0.59 pF will move
Γ
opt
* at Point A to a position on
the unit conductance circle (G=1)
at Point B. A 11.2 nH series
inductor then completes the
match to 50
by moving the
impedance at Point B to the
center of the chart.
The value of the shunt capacitor
is small enough that a short
length of open-circuit transmis-
sion line could be used in place of
the lumped element capacitor.
This saves the expense of a chip
component with the tradeoff of a
small amount of additional circuit
board space. A 0.20-inch length of
open-circuit 50
line is one
choice that would be equivalent
to the 0.59 pF shunt capacitor.
The input matching circuit is
shown in Figure 19.
Results of this step:
The input circuit is:
RF
INPUT
11.2 nH
0.59 pF
Figure 18. Input Circuit.
7. Design of the output
impedance matching network.
Using the circuit file from step 4
(Figure 15),
Touchstone
was used
to calculate the load impedance
Γ
ml
(0.62
∠
+35
°
) of the INA-12063
to achieve maximum power
transfer. The conjugate of
Γ
ml
,
Γ
ml
* (0.62
∠
-35
°
), is plotted as
Point A on the Smith chart in
Figure 19.
A
1
C
B
2
1
-2
B
0.5
0.5
0.2
-0.2
0.2
2
-0.5
-1
ORF
C2
L2
C (50
)
A (
Γ
ml
*)
Figure 19. Output Impedance Match.
The two possible L-C networks
that can be used to match
Γ
ml
* to
50
are either a shunt C-series L
or a shunt L-series C circuit. By
choosing the shunt L-series C
circuit, two of the DC consider-
ations from Step 5 can be satis-
fied: the shunt L can be bypassed
and used to apply the +3 volt
supply to the RF output terminal,
and the series C will serve double
duty as the DC blocking capacitor.
Referring again to Figure 19, a
shunt inductance of 10.8 nH
moves
Γ
ml
* at Point A to Point B
which is on the G1 circle of the
Smith chart. The addition of
1.9pF of series capacitance
completes the impedance trans-
formation to Point C at the center
of the chart. The output matching
circuit is shown in Figure 20.
Results of this step:
The output circuit is:
RF
OUTPUT
11.2 nH
0.59 pF
Figure 20. Output Circuit.
The circuit values from this step
and from Step 6 will be used as a
starting point to be refined in
Step 9 when the circuit is ex-
panded to take practical intercon-
nections and parasitics into
account.
8. PCB Layout.
The results of
the preceding steps and the PCB
layout guidelines in design Step 8
were used to draft the circuit
board layout shown in Figure 21.
Since parasitic effects are mini-
mal, the current source resistor,
R2, can be conveniently placed
directly from the RF output to the
I
bias
connection. A bypass capaci-
tor is added to the shunt stabiliz-
ing resistor, R1 and matching
inductor, L2, on the output. A DC
blocking capacitor, C1, is in-
cluded at the input to complete
the amplifier.
Figure 21. PCB Layout of 900 MHz
LNA.
Results of this step:
PCB layout completed.
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