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參數(shù)資料
| 型號： | IN74LV174N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Registered Transceivers With 3-State Outputs 24-SOIC -40 to 85 |
| 中文描述： | 六角D型觸發(fā)器的復位觸發(fā)器，上升沿觸發(fā) |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 50K |
| 代理商： | IN74LV174N |
TECHNICAL DATA
1
INTEGRAL
Hex D-type flip-flop with reset; positive edge-trigger
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with individual D
inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip–flops simultaneously.
The register is fully edge–triggered. The state of each D input, one set–
up time prior to the LOW–to–HIGH clock transition, is transferred to the
corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently of
clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage elements.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Supply voltage range: 1.2 to 5.5 V
Low input current: 1.0
μ
à; 0.1
μ
à at ò = 25
°
Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V
High Noise Immunity Characteristic of CMOS Devices
IN74LV174
ORDERING INFORMATION
IN74LV174N Plastic
IN74LV174D SOIC
IZ74LV174 Chip
T
A
= -40
°
to 125
°
C for all packages
FUNCTION TABLE
Inputs
Outputs
MR
CP
Dn
Qn
L
X
X
L
H
H
H
H
L
L
H
L
X
no change
H
X
no change
H= high level
L = low level
X = don’t care
LOGIC DIAGRAM
PIN 16=V
CC
PIN 08 = GND
PIN ASSIGNMENT
1
2
3
5
4
6
7
8
GND
16
15
14
13
12
11
10
9
VCC
Q5
MR
Q0
D0
D1
Q1
D2
Q2
D5
D4
Q4
D3
Q3
CP
MR
CP
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