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參數(shù)資料
| 型號： | IN74LS138D |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | 3-to-8-Line Decoder/Demultiplexer |
| 中文描述： | 3至8線譯碼器/解復(fù)用器 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 153K |
| 代理商： | IN74LS138D |
TECHNICAL DATA
1
3-to-8-Line Decoder/Demultiplexer
This schottky-clamped TTL MSI circuit is designed to be used in
high-performance memory-decording or data-routing applications
requiring very short propagation delay time. In high-performance
memory systems this decode can be used to minimize the effects of
system decoding. When employed with high-speed memories utilizing
a fast enable circuit the delay times of this decorder and the enable
time of the memory are usually less than the typical access times of the
memory. This means that the effective system delay introduced by the
schottky-clampled system decoder is negligible.
Designed Specifically for High Speed Memory Decoders and Data
Transmission Systems
Incorporate 3 Enabler Inputs to Simplify Cascading AND/OR Data
Reception
Schottky Clamped for High Performance
IN74LS138
ORDERING INFORMATION
IN74LS138N Plastic
IN74LS138D SOIC
T
A
= 0
°
to 70
°
C
for all packages
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Outputs
CS1 CS2 CS3
A2 A1 A0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H
X H X
L X X
X X X
X X X
X X X
H H H H H H H H
H H H H H H H H
H H H H H H H H
H L L
H L L
H L L
H L L
L L L
L L H
L H L
L H H
L H H H H H H H
H L H H H H H H
H H L H H H H H
H H H L H H H H
H L L
H L L
H L L
H L L
H L L
H L H
H H L
H H H
H H H H L H H H
H H H H H L H H
H H H H H H L H
H H H H H H H L
H = high level (steady state)
L = low level (steady state)
X = don’t care
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
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