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參數(shù)資料
| 型號： | IN74ACT74 |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | DUAL D FLIP-FLOP WITH SET AND RESET |
| 中文描述： | 雙D觸發(fā)器與SET和RESET |
| 文件頁數(shù)： | 4/5頁 |
| 文件大小： | 205K |
| 代理商： | IN74ACT74 |
IN74ACT74
4
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Symbol
Parameter
Guaranteed Limits
25
°
C
-40
°
C to
85
°
C
Min
125
4.0
Unit
Min
145
4.0
Max
11.0
Max
13.0
f
max
t
PLH
Maximum Clock Frequency (Figure 1)
Propagation Delay, Clock to Q or Q
(Figure 1)
Propagation Delay, Clock to Q or Q
(Figure 1)
Propagation Delay, Set or Reset to Q or Q
(Figure 2)
Propagation Delay, Set or Reset to Q or Q
(Figure 2)
Maximum Input Capacitance
MHz
ns
t
PHL
3.5
10.0
3.0
11.5
ns
t
PLH
3.0
9.5
2.5
10.5
ns
t
PHL
3.0
10.0
3.0
11.5
ns
C
IN
4.5
4.5
pF
Power Dissipation Capacitance
Typical @25
°
C,V
CC
=5.0 V
35
C
PD
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF, Input t
r
=t
f
=3.0 ns)
Symbol
Parameter
Guaranteed Limits
25
°
C
-40
°
C to
85
°
C
3.5
Unit
t
su
Minimum Setup Time, Data to Clock (Figure
3)
Minimum Hold Time, Clock to Data (Figure
3)
Minimum Pulse Width, Clock, Set or Reset
(Figures 1,2)
Minimum Recovery Time, Set or Reset to
Clock (Figure 2)
3.0
ns
t
h
1.0
1.0
ns
t
w
5.0
6.0
ns
t
rec
0
0
ns
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|---|---|
| IN74ACT86 | Quad 2-Input Exclusive OR Gate |
| IN74ACT86D | Quad 2-Input Exclusive OR Gate |
| IN74ACT86N | Quad 2-Input Exclusive OR Gate |
| IN74ALS240A | RESISTOR 931 1% .1W |
| IN74LS240AN | Octal Bus Transceivers And Registers With 3-State Outputs 24-SSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IN74ACT74D | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT74N | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:DUAL D FLIP-FLOP WITH SET AND RESET |
| IN74ACT86 | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 2-Input Exclusive OR Gate |
| IN74ACT86D | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 2-Input Exclusive OR Gate |
| IN74ACT86N | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 2-Input Exclusive OR Gate |
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