參數(shù)資料
型號: IN74AC175N
廠商: INTEGRAL JOINT STOCK COMPANY
英文描述: Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS
中文描述: 四D觸發(fā)器與普通時鐘和復位高拖鞋高速硅柵CMOS
文件頁數(shù): 1/5頁
文件大?。?/td> 144K
代理商: IN74AC175N
TECHNICAL DATA
264
Quad D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
The IN74AC175 is identical in pinout to the LS/ALS175,
HC/HCT175. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive-going edge of the Clock input.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A; 0.1
μ
A @ 25
°
C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
IN74AC175
ORDERING INFORMATION
IN74AC175N Plastic
IN74AC175D SOIC
T
A
= -40
°
to 85
°
C for all
packages
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Outputs
Reset
Clock
D
Q
Q
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
no change
X = Don’t care
LOGIC DIAGRAM
PIN 16=V
CC
PIN 8 = GND
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