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參數(shù)資料
| 型號(hào)： | IN74AC112N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS |
| 中文描述： | 雙JK觸發(fā)器的設(shè)置和復(fù)位高速硅柵CMOS |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | IN74AC112N |
TECHNICAL DATA
127
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC112 is identical in pinout to the LS/ALS112,
HC/HCT112. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A; 0.1
μ
A @ 25
°
C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
IN74AC112
ORDERING INFORMATION
IN74AC112N Plastic
IN74AC112D SOIC
T
A
= -40
°
to 85
°
C for all
packages
FUNCTION TABLE
Inputs
Outputs
Set
Reset
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
L
*
H
L
*
L
L
X
X
X
H
H
L
L
No Change
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H
Toggle
H
H
L
X
X
No Change
H
H
H
X
X
No Change
H
H
X
X
No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
LOGIC DIAGRAM
PIN 16=V
CC
PIN 8 = GND
PIN ASSIGNMENT
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| IN74AC125 | 制造商:INTEGRAL 制造商全稱(chēng):INTEGRAL 功能描述:Quad 3-State Noninverting Buffers High-Speed Silicon-Gate CMOS |
| IN74AC125D | 制造商:IKSEMICON 制造商全稱(chēng):IK Semicon Co., Ltd 功能描述:Quad 3-State Noninverting Buffers High-Speed Silicon-Gate CMOS |
| IN74AC125N | 制造商:IKSEMICON 制造商全稱(chēng):IK Semicon Co., Ltd 功能描述:Quad 3-State Noninverting Buffers High-Speed Silicon-Gate CMOS |
| IN74AC132 | 制造商:INTEGRAL 制造商全稱(chēng):INTEGRAL 功能描述:Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High-Performance Silicon-Gate CMOS |
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