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參數(shù)資料
| 型號： | IN7472N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | AND-Gated J-K Master-Slave Flip-Flops with Reset and Clear |
| 中文描述： | 與門控JK主從觸發(fā)器的復位和清除 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 242K |
| 代理商： | IN7472N |
TECHNICAL DATA
IN7472
AND-Gated J-K Master-Slave Flip-
Flops with Reset and Clear
ORDERING INFORMATION
IN7472N Plastic
IN7472D SOIC
T
A
= -10
°
to 70
°
C for all packages
LOGIC DIAGRAM
PIN 14 =V
CC
PIN 7 = GND
PIN ASSIGNMENT
NC - No internal connection
FUNCTION TABLE
Inputs
Output
Reset
Clear
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
*
H
H
*
L
L
X
X
X
H
H
L
L
Q
0
H
Q
0
L
H
H
H
L
H
H
L
H
L
H
H
H
H
H
TOGGLE
X =don’t care
Q
0
= the level of Q before the indicated input conditions were established.
TOGGLE: Each output changes to the complement of its previous level on each
active transition (pulse) of the clock.
*
This configuration is nonstable; that is, it will not persist whenpreset and clear inputs
return to their inactive (high) level.
1
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