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參數(shù)資料
| 型號： | IMIZ9972 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| 中文描述： | 3.3伏，125兆赫，多輸出零延遲緩沖器 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 87K |
| 代理商： | IMIZ9972 |
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Z9972
Cypress Semiconductor Corporation
Document #: 38-07088 Rev. *D
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
Features
Output frequency up to 125 MHz
12 clock outputs: frequency configurable
350 ps max output-to-output skew
Configurable output disable
Two reference clock inputs for dynamic toggling
Oscillator or crystal reference input
Spread Spectrum-compatible
Glitch-free output clocks transitioning
3.3V power supply
Pin-compatible with MPC972
Industrial temperature range: –40°C to +85°C
52-pin TQFP package
Table 1. Frequency Table
[1]
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
F
VCO
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Note:
1.
x = the reference input frequency, 200 MHz < F
VCO
< 480 MHz.
Block Diagram
Pin Configuration
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
XIN
XOUT
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
VDD
F
S
V
Q
V
Q
S
S
Q
V
Q
V
I
S
S
S
S
Q
V
Q
V
Q
V
Q
V
V
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
Z9972
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| IMIZ9972BA | 3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| IMIZ9972BAT | 3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IMIZ9972BA | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 200MHz to 480MHz 52-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:ZERO DELAY BUFFER. 12 OUTPUTS, 125MHZ, 3.3V - Bulk |
| IMIZ9972BAT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 200MHz to 480MHz 52-Pin TQFP T/R 制造商:Rochester Electronics LLC 功能描述:ZERO DELAY BUFFER. 12 OUTPUTS, 125MHZ, 3.3V T/R - Bulk |
| IMIZ9973 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| IMIZ9973AAD | 制造商:IMI 功能描述: |
| IMIZ9973BA | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 52-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:ZERO DELAY BUFFER. 12 OUTPUTS, 125MHZ, PECL INPUT - Bulk |
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