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參數資料
| 型號： | IMIC9827H |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 4/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | IMIC9827H |
C9530
Document #: 38-07033 Rev. *B
Page 4 of 10
2
0
SA1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
SA0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, 42, 43 and 27), 0 =
SMBus Byte 0 bits 1-4, & 6
1
0
0
1
HWSEL
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
0
0
1
1
Byte0, bit5
0
1
0
1
Description
Frequency generated from second PLL
Frequency generated from XIN
Spread @ –1.0%
Spread @ –0.5%
Table 5. Test Table
Test Function Clock
Frequency
Outputs
CLKB
XIN/4
CLKA
XIN/6
REF
XIN
Byte 1: A Bank and REF Clock Control Register
Bit
7
6
5
@Pup
1
1
1
Name
Description
Reserved
Reserved
REF Output Enable
0 = Disable, 1= Enable
CLKA4 Output Enable
0 = Disable, 1= Enable
CLKA3 Output Enable
0 = Disable, 1= Enable
CLKA2 Output Enable
0 = Disable, 1= Enable
CLKA1 Output Enable
0 = Disable, 1= Enable
CLKA0 Output Enable
0 = Disable, 1= Enable
REFEN
4
1
3
1
2
1
1
1
0
1
Byte 2: PCI Register
Bit
7
6
5
4
@Pup
1
1
1
1
Name
Description
Reserved
Reserved
Reserved
CLKB4 Output Enable
0 = Disable, 1= Enable
CLKB3 Output Enable
0 = Disable, 1= Enable
CLKB2 Output Enable
0 = Disable, 1= Enable
CLKB1 Output Enable
0 = Disable, 1= Enable
CLKB0 Output Enable
0 = Disable, 1= Enable
18
3
1
19
2
1
22
1
1
23
0
1
24
Byte 0: Function Select Register
(continued)
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