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參數(shù)資料
| 型號： | IMIB9948 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 39K |
| 代理商： | IMIB9948 |
B9940L
2.5V / 3.3V, 200 MHz, 1:18 Clock Distribution Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07105 Rev. **
5/24/2001
Page 2 of 7
Pin Description
PIN
5
6
3
9, 10, 11, 13, 14,
15, 18, 19, 20,
22, 23, 24, 26,
27, 28, 30, 31,
32
4
NAME
PWR
I/O
I, PU
I, PD
I, PD
O
Description
PECL_CLK
PECL_CLK#
TCLK
Q(17:0)
PECL Input Clock.
PECL Input Clock.
External Reference/Test Clock Input.
Clock Outputs.
VDDC
TCLK_SEL
I, PD
Clock Select Input. When low, PECL clock is selected and when high
TCLK is selected.
3.3V or 2.5V Power Supply for Output Clock Buffers.
3.3V or 2.5V Power Supply
Common Ground
8, 16, 29
7, 21
1, 2, 12, 17, 25
PD = Internal Pull-Down, PU = Internal Pull-Up.
VDDC
VDD
VSS
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