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參數(shù)資料
| 型號： | IMI4350YB |
| 英文描述： | Phase/Frequency Detector |
| 中文描述： | 相位/頻率檢測器 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 48K |
| 代理商： | IMI4350YB |
IMI4343
PHASE DETECTOR
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Rev 1.1
6/9/97
Page 2 of 7
June 1997
CMOS LSI
PLL FREQUENCY SYNTHESIZERS
MAXIMUM RATINGS
Voltage Relative to VSS:
Voltage Relative to VDD
Storage Temperature:
Ambient Temperature:
Recommended Operating Range:
-0.3V to 7V
0.3V
-65oC to 150oC
-45oC to 85 oC
2.7V - 5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)< VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
PIN DESCRIPTIONS
PIN NO.
NAME
DESCRIPTION
1
2
OSCin
OSCout
This input is self biased and is designed to be AC coupled for low level sinewave signals.
Reference signal output can be used in conjunction with OSCin to form an internal crystal
oscillator.
This input is intended to be AC coupled. DC coupling can be used for CMOS logic level
input signals.
Circuit ground.
Circuit positive power supply.
Phase detector output. This signal goes LOW when the feedback frequency is too low.
Phase detector output. This signal goes LOW when the feedback frequency is too high.
Single-ended charge pump output, usually used with passive loop filters. This signal
operates according to the following:
Frequency fv>fr at the phase detector: negative pulses.
Frequency fv<fr at the phase detector: positive pulses.
Frequency fv = fr at the phase detector: high-impedance state.
6
Fin
4
8
3
5
7
VSS
VDD
PHIR
PHIV
Pdout
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