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ILC7080/81
REV. 1.0.7 4/3/03
7
The Effects of ESR (Equivalent
Series Resistance)
The ESR of a capacitor is a measure of the resistance due to the
leads and the internal connections of the component. Typically
measured in m
(milli-ohms) it can increase to ohms in some
cases.
Wherever there is a combination of resistance and current, volt-
ages will be present. The control functions of LDOs use two
voltages in order to maintain the output precisely; V
OUT
and
V
REF
.
With reference to the block diagram in figure 2, V
OUT
is fed
back to the error amplifier and is used as the supply voltage for
the internal components of the 7080/81. So any change in V
OUT
will cause the error amplifier to try to compensate to maintain
V
OUT
at the set level and noise on V
OUT
will be reflected into
the supply of each internal circuit. The reference voltage, V
REF
,
is influenced by the C
NOISE
pin. Noise into this pin will add to
the reference voltage and be fed through the circuit. These fac-
tors will not cause a problem if some simple steps are taken.
Figure 5 shows where these added ESR resistances are present
in the typical LDO circuit.
Figure 5. ESR in C
OUT
and C
NOISE
With this in mind low ESR components will offer better perfor-
mance as LDOs may be exposed to large transients of output
voltage, and current flows through the capacitors in order to fil-
ter these transient swings. ESR is less of a problem with CIN as
the voltage fluctuations at the input will be filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the resis-
tance inherent in the PCB trace. Figure 6 shows where the addi-
tive resistance of the PCB can manifest itself. Again these
resistances may be very small, but a summation of several cur-
rents can develop detectable voltage ripple and will be amplified
by the LDO. Particularly the accumulation of current flows in
the ground plane can develop significant voltages unless care is
taken.
With a degree of care, the ILC7080/81 will yield outstanding
performance.
Printed Circuit Board Layout
Guidelines
As was mentioned in the previous section, to take full advan-
tage of any high performance LDO regulator requires paying
careful attention to grounding and printed circuit board
(PCB) layout.
Figure 6. Inherent PCB resistance
Figure 7 shows the effects of poor grounding and PCB
layout caused by the ESR and PCB resistances and the
accumulation of current flows.
Note particularly that during high output load current, the
LDO regulator’s ground pin and the ground return for C
OUT
and C
NOISE
are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current loop
between C
OUT
, C
NOISE
and the LDO regulator’s ground pin
will degrade performance of the LDO.
Figure 7. Effects of poor circuit layout
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground cur-
rent and noise bypass current return of the LDO regulator.
Note that the key difference here is that C
OUT
and C
NOISE
are
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
ILC7080
ILC7081
V
IN
SOT-23-5
C
IN
ON
OFF
1
2
3
4
5
C
NOISE
RF LDO
TM
Regulator
R*
R*
R
C
V
OUT
C
OUT
I
C
I
OUT
ILC7080
ILC7081
SOT-23-5
ON
OFF
1
2
3
4
5
C
NOISE
R
PCB
ESR
R
PCB
V
IN
V
IN
I
OUT
C
OUT
I
1
I
2
E
V
OUT
R
PCB
R
PCB
R
PCB
C
N
C
OUT
C
IN
ON/OFF
V
OUT
V
IN
G
True GND
(0V)
GND1
GND2
GND3
ILC7080/81
SOT23-5
5
2
3
1
4
I
LOAD
I
LOAD
+ICOUT
+ICNOISE
+IGND
L