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參數(shù)資料
| 型號： | ILC705_N |
| 廠商： | Impala Linear Corporation |
| 英文描述： | MP SUPERVISORY CIRCUIT |
| 中文描述： | 手機監(jiān)控電路 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 74K |
| 代理商： | ILC705_N |
mP Supervisory Circuit
Impala Linear Corporation
3
(408) 574-3939
www.impalalinear.com
Sept 1999
ILC705-708 1.0
Pin Number
ILC705
ILC706
1
Pin
Name
ILC707
ILC708
1
Description
MR
Manual reset input. MR forces RESET to assert when pulled below 0.8V.
An internal pull-up current of 250 mA on this input forces it high when
left floating. This input can also be driven from TTL or CMOS logic.
Power supply input, 5V.
Ground pin, 0 V reference.
Power fail input. Internally connected to the power fail comparator, which
is referenced to 1.25V. The power fail output (PFO) remains high if PFI
is above 1.25V. PFI should be connected to GND or V
OUT
if the power
fail comparator is not used.
Power fail output. The power fail comparator is independent of all other
functions on this device.
Watchdog input. The WDI input monitors microprocessor activity, an
internal watchdog timer resets itself with each transition on the watchdog
input. If the WDI pin is held high or low for longer than the watchdog
timeout period, WDO is forced to active low. The watchdog function can
be disabled by floating the WDI pin.
No Connect.
RESET output. RESET is asserted if either V
CC
goes below the reset
threshold or by a low signal on the manual reset input (MR). RESET
remains asserted for one reset timeout period (200ms) after V
CC
exceeds the reset threshold or after the manual reset pin transitions from
low to high. The watchdog timer will not assert RESET unless WDO is
connected to MR.
Watchdog timer output. The watchdog timer resets itself with each
transition on the watchdog input. If the WDI pin is held high or low for
longer than the watchdog timeout period, WDO is forced low. WDO will
also be forced low if V
CC
is below the reset threshold and will remain low
until V
CC
returns to a valid level.
RESET output. RESET is the compliment of RESET and is asserted if
either V
CC
goes below the reset threshold or by a low signal on the
manual reset input (MR). RESET is suitable for microprocessors
systems that use an active high reset.
Vcc
GND
PFI
2
3
4
2
3
4
PFO
5
5
WDI
6
N/A
N/C
RESET
N/A
6
7
7
WDO
8
N/A
RESET
N/A
8
Pin Functions
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|---|---|
| ILC706 | 制造商:IMPALA 制造商全稱:IMPALA 功能描述:MP SUPERVISORY CIRCUIT |
| ILC7062 | 制造商:IMPALA 制造商全稱:IMPALA 功能描述:SOT-23 CMOS LDO |
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| ILC7062CM25X | 功能描述:低壓差穩(wěn)壓器 - LDO SOT-23 RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| ILC7062CM27X | 功能描述:線性穩(wěn)壓器 - 標(biāo)準(zhǔn) RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負(fù)載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
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