參數(shù)資料
型號(hào)： IH5151MJE
廠商： INTERSIL CORP
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： Dual SPDT, CMOS Analog Switch
中文描述： DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, CDIP16
封裝： CERDIP-16
文件頁(yè)數(shù)： 5/7頁(yè)
文件大小： 155K
代理商： IH5151MJE
5
Typical Applications
Nulling Out Charge Injection
Charge injection (Q
INJ
on spec. sheet) is caused by gate to
drain, or gate to source capacitance of the output switch
MOSFETs. The gates of these MOSFETs typically swing
from -15V to +15V as a rapidly changing pulse; thus this
30V
P-P
pulse is coupled through gate capacitance to output
load capacitance, and the output “step” is a voltage divider
from this combination. For example:
C
LOAD
i.e.,
C
GATE
Thus if you are using a switch in a Sample and Hold
application with C
SAMPLE
= 1000pF, a 45mV
P-P
“Sample-
to-Hold Error Step” will occur.
To null this error step out to zero the circuit in Figure 7 can
be used.
27pF
FIGURE 4A. SUPPLY CURRENT vs FREQUENCY
FIGURE 4B. LOGIC INPUT WAVEFORM
FIGURE 4. SUPPLY CURRENT vs LOGIC FREQUENCY
FIGURE 5. CHARGE INJECTION TEST CIRCUIT
FIGURE 6. t
ON
AND t
OFF
TEST CIRCUIT AND
MEASUREMENT POINTS
Test Circuits and Waveforms
(Continued)
200
20
2
2000
1
10
100
1K
10K
100K
LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz)
I
Q
μ
A
0V
3V
LOGIC INPUT
0.1T
T
=I
T
10nF
0V
3V
LOGIC
INPUT
V
OUT
ANALOG INPUT
V
OUT
A
10pF
1k
±
10V
-15V
t
ON
t
OFF
LOGIC
INPUT
V
OUT
B
10pF
1k
±
10V
+5V
0V
0V
0V
V
OUT
V
OUT
t
ON
t
OFF
+10V
+3V
-10V
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
+15V
Qinject (V
P-P
)
-------------------
30V step.
×
1.5pF, C
LOAD
1000pF, then
=
=
Qinject (V
P-P
)
--------------------
30V step
×
45mV
P-P
=
=
1000pF S&H
CAPACITOR
+5V
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
0V
3V
TTL
STROBE
+15V
-15V
50K
POT
FIGURE 7. ADJUSTABLE CHARGE INJECTION
COMPENSATION CIRCUIT
IH5151
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