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參數(shù)資料
| 型號(hào)： | IFM008G |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Miniature Card(5V 200系列閃速存儲(chǔ)器微型卡) |
| 中文描述： | 512K X 16 FLASH 5V PROM CARD, 150 ns, XMA60 |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 262K |
| 代理商： | IFM008G |
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iFM004G/iFM008G/iFM016G
E
14
PRELIMINARY
Table 6. Basic Command Set Definitions
(9)
Command
Bus
Cycles
Req’d.
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Addr
(2)
Data
(3,4)
Oper
(1)
Addr
(2)
Data
(3,4)
Read Array
1
Write
X
XXFFH
Read Identifier Codes
≥
2
5
Write
X
XX90H
Read
IA
ID
Read Status Register
2
Write
X
XX70H
Read
X
SRD
Clear Status Register
1
Write
X
XX50H
Word Write
2
6, 7
Write
X
XX40H
or
XX10H
Write
WA
WD
Block Erase
2
7
Write
X
XX20H
Write
BA
XXD0H
Block Erase Suspend
1
7
Write
X
XXB0H
Block Erase Resume
1
7
Write
X
XXD0H
Set Block Lock-Bit
2
Write
X
XX60H
Write
BA
XX01H
Clear Block Lock-Bits
2
8
Write
X
XX60H
Write
X
XXD0H
NOTES:
1. Card signal values for the identified bus operations are defined in Table 5.
2. X = Any valid address within the device.
IA = Identifier Code Address:
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3. SRD = Data read from Status Register.
WD = Data to be written at location WA. Data is latched on the rising edge of WE#.
ID = Data read from Identifier Codes.
4. The upper byte of the data bus during command writes is a
“Don’t Care” (X).
5. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Read Identifier Section for read identifier code data.
6. Either XX40H or XX10H are recognized by the WSM as the word-write command setup.
7. The issue of a block erase or write-word command to a locked block will fail.
8. The clear block lock-bits operation simultaneously clears all block lock-bits.
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
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