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| 型號(hào)： | IE-V850ES-G1 |
| 英文描述： | IE-V850ES-G1 User＇s Manual | User＇s Manual[03/2003] |
| 中文描述： | IE瀏覽器- V850ES - G1期用戶手冊|用戶手冊[03/2003] |
| 文件頁數(shù)： | 25/48頁 |
| 文件大小： | 628K |
| 代理商： | IE-V850ES-G1 |
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CHAPTER 3 NOTES ON TARGET SYSTEM DESIGN
User
’
s Manual U16647EJ1V0UM
25
3.2.3
DMS
This is the transfer mode selection signal. The state machine in the debug unit changes according to the level of
the DMS signal. This signal is sampled in synchronization with the rising edge of the DCK signal in the on-chip
debug unit.
Barring a problem arising from the specifications of the target device, pull up this signal to high level. The
connection example for this signal is the same as that shown in
Figure 3-3 DCK Pin Connection Example
.
3.2.4
DDI
This is the data input signal. This signal is sampled in synchronization with the rising edge of the DCK signal in
the on-chip debug unit.
Barring a problem arising from the specifications of the target device, pull up this signal to high level. The
connection example for this signal is the same as that shown in
Figure 3-3 DCK Pin Connection Example
.
3.2.5
DDO
This is the data output signal. This signal is output in synchronization with the falling edge of the DCK signal from
the on-chip debug unit.
Barring a problem arising from the specifications of the target device, pull up this signal to high level.
Figure 3-4. DDO Pin Connection Example
74LV07A
DDO
IE-V850E1-CD-NW
Target device
V
DD
Target system
V
DD
DDO
3.2.6
V
DD
This signal is used for detection of V
DD
of the target system. The interface with the target system (detection range)
is 2.0 V to 5.0 V. If V
DD
from the target system is not detected, the DRST, DCK, DMS, DDI, FLMD0, and RESET pins
go to a high-impedance state.
Figure 3-5. V
DD
Pin Connection Example
74LV07A
IE-V850E1-CD-NW
Target device
V
DD
Target system
3.3 V
1 k
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