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參數(shù)資料
| 型號(hào)： | IDTRC5000-250BS |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 64位微處理器 |
| 英文描述： | MULTI-ISSUE 64-BIT MICROPROCESSOR |
| 中文描述： | 多發(fā)行64位微處理器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 298K |
| 代理商： | IDTRC5000-250BS |
IDT RC5000
COMMERCIAL TEMPERATURE RANGE
3
RC5000 Computational Units
The RC5000 contains the following computational units:
Integer ALU
. The RC5000 implements a full, single-cycle 64-bit ALU for all integer ALU functions other than
multiply and divide. Bypassing is used to support back-to-back ALU operations at the full pipeline rate, without requiring
stalls for data dependencies.
Integer Multiply/Divide Unit
. This unit is separated from the primary ALU, to allow these longer latency operations
to run in parallel with other operations. The pipeline stalls only if an attempt to access the HI or LO registers is made
before the operation completes.
Floating-point ALU
. This unit is responsible for all CP1/CP1X ALU operations other than DIV/SQRT. The unit is
pipelined to allow a single-cycle repeat rate for single-precision operations
Floating-point DIV/SQRT unit
. This unit is separated from the other floating-point ALU, so that these long latency
operations do not prevent the issue of other floating point operations.
In addition, the RC5000 implements separate logical units to implement loads, stores, and branches.
Electrical Specifications
Operating Frequency
The input clock operates in a frequency range of 33MHz to 100MHz. The pipeline frequency for the RC5000 is 2 to
8 times the input clock (up to the maximum for the speed grade of CPU).
THERMAL CONSIDERATIONS
The RC5000 utilizes special packaging techniques, to improve the thermal properties of high-speed processors.
The RC5000 is packaged using cavity down packaging in a 223-pin PGA package with integral thermal slug, and a
272-pin BGA package. These packages effectively dissipate the power of the CPU, increasing device reliability.
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one cycle
Key to Figure
1I-1R
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Instruction cache access
Instruction virtual to physical address translation
Data cache access and load align
Data virtual to physical address translation
Virtual to physical address translation
Register file read
Bypass calculation
Instruction decode
Branch address calculation
Issue or slip decision
Integer add, logical, shift
Data virtual address calculation
Store align
Branch decision
Register file write
Figure 1. R5000 Integer Pipeline Stages
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| IDTRC5000-250G | MULTI-ISSUE 64-BIT MICROPROCESSOR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTRC5000-250G | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:MULTI-ISSUE 64-BIT MICROPROCESSOR |
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