參數資料
型號： IDTQS74FCT2841ATSO
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通用總線功能
英文描述： HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH
中文描述： FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24
封裝： SOIC-24
文件頁數： 2/6頁
文件大?。?/td> 55K
代理商： IDTQS74FCT2841ATSO
2
INDUSTRIAL TEMPERATURE RANGE
IDTQS74FCT2841AT/BT/CT
HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH
SOIC/ QSOP
TOP VIEW
2
3
1
V
CC
20
19
18
15
16
23
22
24
21
17
Y
2
Y
4
Y
3
Y
6
Y
5
Y
1
Y
7
Y
8
13
14
LE
Y
9
Y
0
D
4
D
5
D
3
D
7
D
6
D
1
D
2
D
8
9
10
5
6
7
4
8
11
12
GND
OE
D
0
D
9
PIN CONFIGURATION
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
Description
Max
Unit
V
°C
mA
mA
mA
Termnal Voltage with Respect to GND
Storage Temperature
DC Output Current Max Sink Current/Pin
Input Diode Current, V
IN
< 0
Output Diode Current, V
OUT
< 0
–0.5 to +7
–65 to +150
120
–20
–50
ABSOLUTE MAX IMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
NOTES:
1. This parameter is measured at characterization but not tested.
2. Pins 1-11, 13.
3. Pins 15-22.
4. Pins 14, 23.
PIN DESCRIPTION
Pin Names
I/O
Dx
LE
Description
I
I
Latch Data Inputs
The latch enable input. The latches are transparent when
LE is HIGH. Input data is latched on the HIGH-to-LOW
transition.
3-State Latch Outputs
The output enable control. When
OE
is LOW, the outputs
are enabled. When
OE
is HIGH, the outputs Yx are in
high-impedance (off) state.
Yx
OE
O
I
Symbol
C
IN
(2)
C
OUT
(3)
C
OUT
(4)
Parameter
(1)
Input Capacitance
Output Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
OUT
= 0V
Typ.
4
6
4
Max.
—
—
—
Unit
pF
pF
pF
FUNCTION TABLE
(1)
Inputs
Internal
Outputs
OE
LE
Dx
Value Qx
Yx
Function
H
H
L
L
Z
High-Z
H
H
H
H
Z
High-Z
H
L
X
NC
Z
Latched (High-Z)
L
H
L
L
L
Transparent
L
H
H
H
H
Transparent
L
L
X
NC
NC
Latched
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
NC = No Change
Z = High-Impedance
LOGIC SY MBOL
Dx
LE
OE
D
Q
Yx
LE
10
10
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