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參數(shù)資料
| 型號(hào)： | IDTQS5LV919-133J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 111K |
| 代理商： | IDTQS5LV919-133J |
8
INDUSTRIALTEMPERATURERANGE
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,
Q2, Q3 and Q4).
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4,
Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
Figure 2c. Wiring Diagram and Frequency Relationships with
Q2 Output Feedback
Figure 2b. Wiring Diagram and Frequency Relationships with
Q4 Output Feedback
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEED BACK
REF_SEL
SYNC(0)
VCC(AN)
GND(AN)
Q4
Q5
2Q
LOW
50 MHz signal
12.5 MHz feedback signal
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 MHz
input
PE
QS5LV919
RST
OE/
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEED BAC K
REF_SEL
SYNC(0)
VCC(AN)
GND(AN)
Q4
Q5
2Q
LOW
50 MHz signal
25 MHz feedback signal
HIGH
25 MHz
"Q"
Clock
Outputs
25 MHz
input
12.5 MHz
signal
PE
QS5LV919
RST
OE/
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,the2QoutputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Notethatwith2Qasfeedback,themaximuminputfrequencyis100MHzforFS
= HIGH
Figure 2a. Wiring Diagram and Frequency Relationships with 2Q
Output Feedback
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEED BAC K
REF_SEL
SYNC(0)
VCC(AN)
GND(AN)
Q4
Q5
2Q
LOW
50 MHz feedback signal
HIGH
25 M Hz
"Q"
Clock
Outputs
50 M Hz
input
12.5 MHz
input
PE
QS5LV919
RST
OE/
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,theQ4outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
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