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參數(shù)資料
| 型號： | IDTQS52805ATSO8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 93K |
| 代理商： | IDTQS52805ATSO8 |
1
QS52805T/AT
GUARANTEEDLOWSKEWCMOSCLOCKDRIVER/BUFFER
INDUSTRIALTEMPERATURERANGE
AUGUST 2000
1999
Integrated Device Technology, Inc.
DSC-5480/-
c
QS52805T/AT
ADVANCE
INFORMATION
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
OEA
INA
INB
OA 5
OA 1
5
MON
OB 5
OB 1
OEB
DESCRIPTION
The QS52805T clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of five non-inverting outputs. This device provides low propagation delay
buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
The QS52805T has on-chip series termination resistors for lower noise
clock signals. The QS52805T series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise sensitive
clock distribution circuits. These clock buffer products are designed for use
in high-performance workstations and in embedded and personal comput-
ing systems. Several devices can be used in parallel or scattered throughout
a system for guaranteed low skew, system-wide clock distribution networks.
The QS52805T is characterized for operation at -40°C to +85°C.
NOTE: This device has 25
series termination resistors on each clock output including monitor.
FEATURES:
10 output, low skew signal buffer
Guaranteed low skew:
0.7ns output skew (same bank)
0.9ns output skew (different bank)
1ns part-to-part skew
25 on-chip resistors available for low noise
Input hysteresis for better noise margin
Monitor output
Undershoot clamp diodes on all inputs
Std. and A speed grades
Available in QSOP and SOIC packages
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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