參數(shù)資料
型號(hào)： IDTQS4A101QG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 3/7頁
文件大?。?/td> 0K
描述： IC SWITCH QUAD SPST 16QSOP
標(biāo)準(zhǔn)包裝： 291
功能： 開關(guān)
電路： 4 x SPST
導(dǎo)通狀態(tài)電阻： 17 歐姆
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 5V
電流 - 電源： 3µA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 管件
其它名稱： 800-1775
800-1775-5
800-1775-ND
QS4A101QG
3
IDTQS4A101
HIGH-PERFORMANCECMOSANALOGFOUR-CHANNELSPSTSWITCH
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5V ± 5%
Symbol
Parameter
Test Conditions
Min.
Typ.(1) Max.
Unit
Analog Switch
VIN
Analog Signal Range(2)
-0.5
1
Vcc - 1
V
rDS(ON)
Drain-source ON resistance(2,3)
Vcc = Min., VIN = 0V
, ION = 30mA
—
5
7
Vcc = Min., VIN = 2.4V
, ION = 15mA
—
13
17
IC(OFF)
Channel Off Leakage Current
A = Vcc or 0V, B = 0V or Vcc,
E = Vcc
—
1
—
nA
IC(ON)
Channel On Leakage Current
A = B = 0V
—
1
—
nA
(each channel is turned on sequentially)
Digital Control
VIH
Input HIGH Voltage
Guaranteed Logic HIGH for Control Pins
2
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW for Control Pins
—
0.8
V
Dynamic Characteristics
tON(E)
Enable Turn-On Time
RL = 1K
, CL = 100pF
0.5
—
6.5
ns
E to A, B
(See Switching Time)
tOFF(E)
Enable Turn-Off Time
RL = 1K
, CL = 100pF
0.5
—
6
ns
E to A, B
(See Switching Time)
tPD
Group Delay(2,4a)
RL = 1K
, CL = 100pF
—
250
ps
f3dB
-3dB Bandwidth
VIN = 0 to 1V, 1Vp-p, RL = 75
—
1.4
—
GHz
Off-isolation
VIN = 0 to 1V, 1Vp-p, RL = 75
, f = 5.5MHz
—
-80
—
dB
XTALK
Crosstalk
VIN = 0 to 1V, 1Vp-p, RL = 75
, f = 30MHz
—
-75
—
dB
C(OFF)
Switch Off Capacitance
E = Vcc, VIN = VOUT = 0V
—
5
—
pF
C(ON)
Switch On Capacitance
E = 0V, VIN = VOUT = 0V
—
10
—
pF
QCI
Charge Injection
—
1.5
—
pC
NOTES:
1. Typical values are at VCC = 5.0V, TA = 25°C.
2. Max value is guaranteed but not production tested.
3. Measured by voltage drop between A and C pins at indicated current through the switch ON resistance is determined by the lower of the voltages on the two (A, B)
pins.
4. The bus switch contributes no group delay other than the RC delay of the ON resistance of the switch and load capacitance. Group delay of the bus switch, when
used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
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