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參數(shù)資料
| 型號： | IDTCSPT857DBVI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 |
| 封裝： | VFBGA-56 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 138K |
| 代理商： | IDTCSPT857DBVI8 |
1
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2003
Integrated Device Technology, Inc.
DSC-6835/2
c
IDTCSPT857D
ADVANCE
INFORMATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V - 2.6V PHASE LOCKED
LOOP DIFFERENTIAL 1:10
SDRAM CLOCK DRIVER
OCTOBER 2003
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
1 to 10 differential clock distribution
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications requiring improved output crosspoint
voltage
Operating frequency: 60MHz to 220MHz
Very low skew:
– <100ps for PC1600 - PC2700
– <75ps for PC3200
Very low jitter:
– <75ps for PC1600 - PC2700
– <50ps for PC3200
2.5V AVDD and 2.5V VDDQ for PC1600-PC2700
2.6V AVDD and 2.6V VDDQ for PC3200
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-
pin VFBGA packages
DESCRIPTION:
TheCSPT857DisaPLLbasedclockdriverthatactsasazerodelaybuffer
todistributeonedifferentialclockinputpair(CLK,CLK)to10differentialoutput
pairs(Y[0:9],Y[0:9])andonedifferentialpairoffeedbackclockoutput(FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the input frequency falls below
approximately20MHz,thedevicewillenterpowerdownmode. Inthismode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
aretristated,resultinginacurrentconsumptionoflessthan200
A.
TheCSPT857Drequiresnoexternalcomponentsandhasbeenoptimised
forverylowI/Ophaseerror,skew,andjitter,whilemaintainingfrequencyand
duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857D,
designedforuseinbothmoduleassembliesandsystemmotherboardbased
solutions,providesanoptimumhigh-performanceclocksource.
The CSPT857D is available in Commercial Temperature Range (0°C to
+70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering
Informationfordetails.
APPLICATIONS:
Meets or exceeds JEDEC standard JESD 82-1A for registered
DDR clock driver
Meets proposed DDR1-400 specification
For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
PC2700 (DDR333), PC3200 (DDR400)
Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,
SSTVF16859, SSTVN16859, DDR1 register, provides complete
solution for DDR1 DIMMs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPT857DNL | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DNLG | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTCSPT857DNLG8 | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTCSPT857DNLI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DPA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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