參數(shù)資料
型號(hào)： IDTCSPT857CPAGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
中文描述： 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝： GREEN, TSSOP-48
文件頁(yè)數(shù)： 5/15頁(yè)
文件大?。?/td> 148K
代理商： IDTCSPT857CPAGI
5
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (TSSOP/TV SOP)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN
, FBIN
FBOUT,
FBOUT
GND
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
PWRDWN
V
DDQ
4, 11, 12, 15, 21, 28, 34, 38, 45
Y
[0:9]
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
Y
[0:9]
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Pin Number
17
16
13, 14
35, 36
32, 33
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
37
PIN DES CRIPT ION (V FBGA)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN
, FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
H1
G2
F1, F2
F5, F6
H6, G5
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
E6
B3, B4, E1, E2, E5, G1, G6, J3, J4
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
AV
DD
Supply Voltage
V
DDQ
I/O Supply Voltage
Min.
Typ.
V
DDQ
2.5
2.6
Max.
2.7
2.7
2.7
+85
Unit
V
V
V
DDQ
– 0.12
2.3
2.5
-40
PC1600-PC2700
PC3200
T
A
Operating Free-Air Temperature
°
C
PIN DES CRIPT ION (MLF)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN
, FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
9
8
5, 6
25, 26
21, 22
1, 10
27
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
4, 7, 13, 18, 23, 24, 28, 33, 38
3, 12, 14, 17, 19, 29, 32, 34, 37, 39
2, 11, 15, 16, 20, 30, 31, 35, 36, 40
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDTCSPT857CPAI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857CPF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857CPFI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857D 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857DBV 制造商: 功能描述: 制造商:undefined 功能描述:
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