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參數(shù)資料
| 型號： | IDTCSPT857CNL |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 封裝： | VFQFPN-40 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 148K |
| 代理商： | IDTCSPT857CNL |
7
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE FOR PC3200
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C; Industrial: T
A
= -40°C to +85°C
Symbol
Parameter
Conditions
V
IK
Input Clamp Voltage (All Inputs)
V
DDQ
= 2.5V, I
I
= -18mA
V
IL (dc)
Static Input LOW Voltage
PWRDWN
V
IH (dc)
Static Input HIGH Voltage
PWRDWN
V
IL (ac)
Dynamc Input LOW Voltage
CLK,
CLK
, FBIN,
FBIN
V
IH (ac)
Dynamc Input HIGH Voltage
CLK,
CLK
, FBIN,
FBIN
V
OL
Output LOW Voltage
A
VDD
/V
DDQ
= Mn., I
OL
= 100
μ
A
A
VDD
/V
DDQ
= Mn., I
OL
= 12mA
V
OH
Output HIGH Voltage
A
VDD
/V
DDQ
= Mn., I
OH
= -100
μ
A
A
VDD
/V
DDQ
= Mn., I
OH
= -12mA
V
IX
Input Differential Cross Voltage
V
ID(DC) (1)
DC Input Differential Voltage
V
ID(AC) (1)
AC Input Differential Voltage
I
IN
Input Current
V
DDQ
= 2.7V, V
I
= 0V to 2.7V
I
DDPD
Power-Down Current on V
DDQ
and A
VDD
A
VDD
/V
DDQ
= Max., CLK = 0MHz or
PWRDWN
= L
I
DDQ
Dynamc Power Supply Current on V
DDQ
A
VDD
/V
DDQ
= Max., CLK = 200MHz, 120
/14pF
A
VDD
/V
DDQ
= Max., CLK = 200MHz, 120
/14pF
I
ADD
Dynamc Power Supply Current on A
VDD
A
VDD
/V
DDQ
= Max., CLK = 200MHz
Min.
– 0.3
1.7
1.7
Typ.
Max.
– 1.2
0.7
Unit
V
V
V
DDQ
+ 0.3
0.7
V
DDQ
0.1
0.6
V
V
V
DDQ
– 0.1
1.7
V
DDQ
/2 – 0.2
0.36
0.7
V
V
DDQ
/2 + 0.2
V
DDQ
+ 0.6
V
DDQ
+ 0.6
±10
200
360
300
12
V
V
V
μ
A
μ
A
mA
100
320
250
mA
NOTE:
1. V
ID
is the magnitude of the difference between the input level on CLK and the input level on
CLK
.
TIMING REQUIREMENTS FOR PC3200
Symbol
Parameter
f
CLK
Operating Clock Frequency
(1,2)
Application Clock Frequency
(1,3)
t
DC
Input Clock Duty Cycle
t
L
Stabilization Time
(4)
Min.
60
60
40
Max.
220
220
60
100
Unit
MHz
MHz
%
μ
s
NOTES:
1.
2.
3.
4.
The PLL will track a spread spectrumclock input.
Operating clock frequency is the range over which the PLL will lock, but may not meet all timng specifications.
Application clock frequency is the range over which timng specifications apply.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
T IMING REQUIREMENT S FOR PC1600 - PC2700
Symbol
Parameter
f
CLK
Operating Clock Frequency
(1,2)
Application Clock Frequency
(1,3)
t
DC
Input Clock Duty Cycle
t
L
Stabilization Time
(4)
Min.
60
60
40
Max.
200
200
60
100
Unit
MHz
MHz
%
μ
s
NOTES:
1.
2.
3.
4.
The PLL will track a spread spectrumclock input.
Operating clock frequency is the range over which the PLL will lock, but may not meet all timng specifications.
Application clock frequency is the range over which timng specifications apply.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
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| IDTCSPT857C | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPT857CNLG | 功能描述:IC SDRAM CLK DVR 1:10 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CNLG8 | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CNLGI | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CNLGI8 | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CNLI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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