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參數(shù)資料
| 型號： | IDTCSPT857C |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | 為2.5V - 2.6V的鎖相環(huán)微分1:10 SDRAM的時鐘驅動器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 148K |
| 代理商： | IDTCSPT857C |
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
SWITCHING CHARACTERISTICS FOR PC1600 - PC2700
Symbol
Description
t
PLH(1)
LOW to HIGH Level Propagation Delay Time
t
PHL(1)
HIGH to LOW Level Propagation Delay Time
t
JIT(PER)
Jitter (period), see figure 6
Test Conditions
Test mode, CLK to any output
Test mode, CLK to any output
66MHz
100/ 133/ 167/ 200 MHz
66MHz
100/ 133/ 167/ 200 MHz
66MHz
100/ 133/ 167/ 200 MHz
100/ 133/ 167/ 200 MHz (20% to 80%)
Min.
Typ.
(1)
4.5
4.5
Max.
Unit
ns
ns
ps
– 90
– 75
– 180
– 75
– 160
– 100
1
1
– 50
90
75
180
75
160
100
2.5
4
50
75
900
V
DDQ
/2
+ 0.15
t
JIT(CC)
Jitter (cycle-to-cycle), see figure 3
ps
t
JIT(HPER)
Half-Period Jitter, see figure 7
ps
t
SLR(O)
t
SLR(I)
t
(
)
t
SK(O)
t
R,
t
F
V
OX(5)
Output Clock Slew Rate (Single-Ended)
Input Clock Slew Rate
Static Phase Offset, see figure 4
(2,3)
Output Skew, see figure 5
Output Rise and Fall Times (20% to 80%)
Output Differential Voltage
V/ns
V/ns
ps
ps
ps
V
66/ 100/ 133/ 167/ 200 MHz
Load: 120
/ 14pF
Differential outputs are termnated
with 120
650
V
DDQ
/2
– 0.15
The PLL on the CSPT857 will meet all the above test parameters while supporting SSC synthesizers
(4)
with the following parameters:
SSC
Modulation Frequency
SSC
Clock Input Frequency Deviation
f
3dB
PLL Loop Bandwidth
30
0
5
50
-0.5
KHz
%
MHz
NOTES:
1.
2.
3.
4.
5.
Refers to transition of non-inverting output.
Static phase offset does not include jitter.
t(
φ
) is measured with input clock slew rate t
SLR
(
I
) = 2V/ns and an input differential voltage V
ID
of 1.75V.
The SSC requirements meet the Intel PC100 SDRAMRegistered DIMMspecification.
V
OX
is specified at the SDRAMclock input or test load.
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| IDTCSPT857CBV | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CBVI | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNLG | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNLGI | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPT857CBV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CBVG | 功能描述:IC PLL CLK DVR SDRAM 56-VFBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CBVG8 | 功能描述:IC PLL CLK DVR SDRAM 56-VFBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CBVI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNL | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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