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參數(shù)資料
| 型號： | IDTCSP5993-2Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 115K |
| 代理商： | IDTCSP5993-2Q |
1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP5993
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
GND/sOE
1Q0
Skew
Select
1Q1
1F1:0
3
2Q0
Skew
Select
2Q1
2F1:0
FS
3
REF
PLL
FB
3
3Q0
Skew
Select
3Q1
3F1:0
3
4Q0
4Q1
3
VCCQ /PE
FEBRUARY 2000
2000
Integrated Device Technology, Inc.
DSC-5811/-
c
IDTCSP5993
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK
DESCRIPTION:
The CSP5993 is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The CSP5993 has six programmable skew
outputs and two zero skew outputs. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
FEATURES:
3 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 6.25MHz to 100MHz
2x, 4x, 1/2, and 1/4 outputs
5V with TTL outputs
3 skew grades:
CSP5993-2: tSKEW0<250ps
CSP5993-5: tSKEW0<500ps
CSP5993-7: tSKEW0<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA IOLhigh drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50
terminatedlines
Available in QSOP Package
FUNCTIONAL BLOCK DIAGRAM
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