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參數(shù)資料
| 型號： | IDT89HPES8NT2ZBBCG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 0K |
| 描述： | IC PCI SW 8LANE 2PORT 324-CABGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | PRECISE™ |
| 類型： | PCI Express 開關(guān) - Gen1 |
| 應(yīng)用： | 服務(wù)器，儲存，通信，嵌入式，消費品 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-LBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CABGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 89HPES8NT2ZBBCG |
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January 5, 2009
IDT 89HPES8NT2 Data Sheet
Figure 2 PCIe System Interconnect Architecture Block Diagram
Pin Description
The following tables list the functions of the pins provided on the PES8NT2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PEALREV
I
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PEARP[3:0]
PEARN[3:0]
I
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PEATP[3:0]
PEATN[3:0]
O
PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PECLREV
I
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PECRP[3:0]
PECRN[3:0]
I
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PECTP[3:0]
PECTN[3:0]
O
PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
PES8NT2
CPU
PCIe System Interconnect Switch
PES8NT2
CPU
PES8NT2
CPU
Embedded
FC
CPU
Embedded
SATA / SAS
CPU
Embedded
GbE / 10GigE
CPU
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| IDT89HPES8NT2ZBBCG8 | 功能描述:IC PCI SW 8LANE 2PORT 324-CABGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89HPES8T5AZBBC | 功能描述:IC PCI SW 8LANE 5PORT 196-CABGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89HPES8T5AZBBC8 | 功能描述:IC PCI SW 8LANE 5PORT 196-CABGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89HPES8T5AZBBCG | 功能描述:IC PCI SW 8LANE 5PORT 196-CABGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89HPES8T5AZBBCG8 | 功能描述:IC PCI SW 8LANE 5PORT 196-CABGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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