參數(shù)資料
型號: IDT89HPES24NT3ZBBXG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/31頁
文件大?。?/td> 0K
描述: IC PCI SW 24LANE 3PORT 420-SBGA
標準包裝: 40
系列: PRECISE™
類型: PCI Express 開關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲存,通信,嵌入式,消費品
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA
供應(yīng)商設(shè)備封裝: 420-SBGA(27x27)
包裝: 托盤
其它名稱: 89HPES24NT3ZBBXG
13 of 31
January 5, 2009
IDT 89HPES24NT3 Data Sheet
Figure 5 JTAG AC Timing Waveform
Recommended Operating Supply Voltages
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES24NT3, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the
power-up sequence.
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDCORE
Internal logic supply
0.9
1.0
1.1
V
VDDI/O
I/O supply except for SerDes LVPECL/CML
3.0
3.3
3.6
V
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit Termina-
tion Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
V
Table 12 PES24NT3 Operating Voltages
Tpw_16d
Tdz_16c
Tdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
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