參數(shù)資料
型號： IDT82V3280DQG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 68/171頁
文件大?。?/td> 0K
描述： IC PLL WAN SE STRATUM 2 100-TQFP
標準包裝： 1
類型： 時鐘/頻率發(fā)生器，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 14:9
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應商設備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
其它名稱： 82V3280DQG
IDT82V3280
WAN PLL
Pin Description
16
December 9, 2008
A0 / SDI
A1 / CLKE
A2
A3
A4
A5
A6
69
68
67
66
65
64
63
I
pull-down
CMOS
A[6:0]: Address Bus
In ERPOM, Intel and Motorola modes, these pins are the address bus of the microprocessor
interface.
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
CLKE: SCLK Active Edge Selection
In Serial mode, this pin selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
In Multiplexed mode, A0/SDI, A1/CLKE and A[6:2] pins should be connected to ground.
In Serial mode, A[6:2] pins should be connected to ground.
AD0 / SDO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
83
82
81
80
79
78
77
76
I/O
pull-down
CMOS
AD[7:0]: Address / Data Bus
In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the micro-
processor interface.
In Multiplexed mode, these pins are the bi-directional address/data bus of the microproces-
sor interface.
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
In Serial mode, AD[7:1] pins should be connected to ground.
WR
71
I
pull-up
CMOS
WR: Write Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation.
In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to ini-
tiate a read operation.
In EPROM and Serial modes, this pin should be connected to ground.
RD
72
I
pull-up
CMOS
RD: Read Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation.
In EPROM, Motorola and Serial modes, this pin should be connected to ground.
ALE / SCLK
73
I
pull-down
CMOS
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description 1
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