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參數(shù)資料
| 型號(hào)： | IDT82V3280DQG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | WAN PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | GREEN, TQFP-100 |
| 文件頁(yè)數(shù)： | 6/167頁(yè) |
| 文件大小： | 1039K |
| 代理商： | IDT82V3280DQG |
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List of Tables
6
June 19, 2006
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 19
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 20
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 22
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 24
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 25
Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 25
Table 8: External Fast Selection ................................................................................................................................................................................ 25
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 26
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 27
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 27
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 28
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 29
Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 30
Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 31
Table 16: T4 DPLL Operating Mode Control ............................................................................................................................................................... 33
Table 17: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 33
Table 18: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 34
Table 19: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 35
Table 20: Holdover Frequency Offset Read ................................................................................................................................................................ 35
Table 21: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 36
Table 22: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 38
Table 23: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 39
Table 24: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 40
Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 APLL .............................................................................................................................. 41
Table 26: Outputs on OUT8 & OUT9 ........................................................................................................................................................................... 41
Table 27: Synchronization Control ............................................................................................................................................................................... 42
Table 28: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 43
Table 29: Device Master / Slave Control ..................................................................................................................................................................... 44
Table 30: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 45
Table 31: Microprocessor Interface ............................................................................................................................................................................. 48
Table 32: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 49
Table 33: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 50
Table 34: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 51
Table 35: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 52
Table 36: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 53
Table 37: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 54
Table 38: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 55
Table 39: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 56
Table 40: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 57
Table 41: JTAG Timing Characteristics ....................................................................................................................................................................... 58
Table 42: Register List and Map .................................................................................................................................................................................. 59
Table 43: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 149
Table 44: Thermal Data ............................................................................................................................................................................................. 149
Table 45: Absolute Maximum Rating ......................................................................................................................................................................... 150
Table 46: Recommended Operation Conditions ........................................................................................................................................................ 150
Table 47: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 152
Table 48: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 153
List of Tables
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| IDT82V3280PF | WAN PLL |
| IDT82V3280PFG | WAN PLL |
| IDT82V3288 | WAN PLL |
| IDT82V3288BC | WAN PLL |
| IDT82V3288BCG | WAN PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IDT82V3280DQG8 | 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3280EQG | 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3280EQG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP |
| IDT82V3280EQGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
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