參數(shù)資料
型號： IDT82V3255TFG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： GREEN, TQFP-64
文件頁數(shù)： 27/127頁
文件大?。?/td> 868K
代理商： IDT82V3255TFG
IDT82V3255
WAN PLL
Functional Description
27
June 19, 2006
3.8.2.2
Non-Revertive Switch (T0 only)
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected. See
Table 9
for the ‘n’ assigned to
each input clock.
3.8.3
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
The
selected
input
clock
is
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits. Note if the T4 selected
input clock is a T0 DPLL output, it can not be indicated by these bits.
The qualified input clocks with the three highest priorities are indi-
cated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_
PRIORITY_VALIDATED[3:0]
bits
_VALIDATED[3:0] bits respectively. If more than one input clock has the
same priority, the input clock with the smallest ‘n’ is indicated by the
HIGHEST_PRIORITY_VALIDATED[3:0] bits. See
Table 9
for the ‘n’
assigned to the input clock.
and
the
THIRD_PRIORITY
When the device is configured in Automatic selection and Revertive
switch
is
enabled,
the
input
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
clock
indicated
by
the
When all the input clocks for T4 path changes to be unqualified, the
INPUT_TO_T4
1
bit will be set. If the INPUT_TO_T4
2
bit is ‘1’, an inter-
rupt will be generated.
Table 15: Related Bit / Register in Chapter 3.8
Bit
Register
Address (Hex)
T0_FOR_T4
T4_INPUT_SEL_CNFG
INPUT_VALID1_STS, INPUT_VALID2_STS
51
INn_CMOS
1
(n = 1, 2 or 3) / INn_DIFF
1
(n = 1 or 2)
INn_CMOS
2
(n = 1, 2 or 3) / INn_DIFF
2
(n = 1 or 2)
INn_CMOS
3
(n = 1, 2 or 3) / INn_DIFF
3
(n = 1 or 2)
INn_CMOS_NO_ACTIVITY_ALARM
(n = 1, 2 or 3)
INn_CMOS_FREQ_HARD_ALARM
(n = 1, 2 or 3)
INn_CMOS_PH_LOCK_ALARM (
n = 1, 2 or 3
)
INn_DIFF_NO_ACTIVITY_ALARM
(n = 1 or 2)
INn_DIFF_FREQ_HARD_ALARM
(n = 1 or 2)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
IN_NOISE_WINDOW
ULTR_FAST_SW
LOS_FLAG_TO_TDO
T0_MAIN_REF_FAILED
1
T0_MAIN_REF_FAILED
2
INPUT_TO_T4
1
INPUT_TO_T4
2
REVERTIVE_MODE
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
CURRENTLY_SELECTED_INPUT[3:0]
HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_PRIORITY_VALIDATED[3:0]
THIRD_PRIORITY_VALIDATED[3:0]
T4_T0_SEL
Note: *
The setting in the 27, 28, 2A, 4E and 4F registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
4A, 4B
INTERRUPTS1_STS, INTERRUPTS2_STS
0D, 0E
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
10, 11
IN1_IN2_CMOS_STS, IN3_CMOS_STS
44, 47
IN1_IN2_DIFF_STS
45
PHASE_MON_PBO_CNFG
78
MON_SW_PBO_CNFG
0B
INTERRUPTS2_STS
0E
INTERRUPTS2_ENABLE_CNFG
11
INTERRUPTS3_STS
0F
INTERRUPTS3_ENABLE_CNFG
INPUT_MODE_CNFG
12
09
IN1_IN2_CMOS_SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
27 *, 2A *
28 *
PRIORITY_TABLE1_STS
4E *
PRIORITY_TABLE2_STS
4F *
T4_T0_REG_SEL_CNFG
07
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