- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2000 > IDT82V3255TFG (IDT, Integrated Device Technology Inc)IC PLL WAN SMC STRATUM 3 64-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT82V3255TFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 65/132頁 |
| 文件大小： | 0K |
| 描述： | IC PLL WAN SMC STRATUM 3 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，PECL |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 82V3255TFG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁當(dāng)前第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁
IDT82V3255
WAN PLL
Functional Description
38
December 3, 2008
3.13.2
FRAME SYNC OUTPUT SIGNALS
An 8 kHz and a 2 kHz frame sync signals are output on the
FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and
2K_EN bits respectively. They are CMOS outputs.
The two frame sync signals are derived from the T0 APLL output and
are aligned with the output clock. They can be synchronized to one of
the three frame sync input signals.
One of the three frame sync input signals is selected, as determined
by the SYNC_BYPASS bit and the T0 selected input clock, as shown in
If the selected frame sync input signal with respect to the T0 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the selected frame sync input sig-
nal is disabled to synchronize the frame sync output signals. The exter-
nal sync alarm is cleared once the selected frame sync input signal with
respect to the T0 selected input clock is within the limit. If it is within the
limit, whether the selected frame sync input signal is enabled to synchro-
nize the frame sync output signal is determined by the SYNC_BYPASS
bit, the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. Refer to
Table 28 for details.
When the selected frame sync input signal is enabled to synchronize
the frame sync output signal, it should be adjusted to align itself with the
T0 selected input clock. Nominally, the falling edge of the selected frame
sync input signal is aligned with the rising edge of the T0 selected input
clock. The selected frame sync input signal may be 0.5 UI early/late or 1
UI late due to the circuit and board wiring delays. Setting the sampling of
the selected frame sync input signal by the SYNC_PHn[1:0] bits (n = 1,
2 or 3 corresponding to EX_SYNC1, EX_SYNC2 or EX_SYCN3 respec-
tively) will compensate this early/late. Refer to Figure 8 to Figure 11.
The EX_SYNC_ALARM_MON bit indicates whether the selected
frame sync input signal is in external sync alarm status. The external
sync alarm is indicated by the EX_SYNC_ALARM 1 bit. If the
EX_SYNC_ALARM 2 bit is ‘1’, the occurrence of the external sync alarm
will trigger an interrupt.
The 8 kHz and the 2 kHz frame sync output signals can be inverted
by setting the 8K_INV and 2K_INV bits respectively. The frame sync out-
puts can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL
and 2K_PUL bits respectively. When they are pulsed, the pulse width is
defined by the period of OUT2; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 2K_8K_PUL_POSITION bit.
Figure 8. On Target Frame Sync Input Signal Timing
Figure 9. 0.5 UI Early Frame Sync Input Signal Timing
Table 27: Frame Sync Input Signal Selection
SYNC_BYPASS T0 Selected Input Clock
Selected Frame Sync Input
Signal
0
don’t-care
EX_SYNC1
1
IN1_CMOS or IN1_DIFF
EX_SYNC1
IN2_CMOS or IN2_DIFF
EX_SYNC2
IN3_CMOS
EX_SYNC3
none
Table 28: Synchronization Control
SYNC_BYPASS
AUTO_EXT_SYNC_EN
Synchronization
0
don’t-care
0
Disabled
01
Enabled
1
Disabled
1
don’t-care
Enabled
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82V3280APFG | IC PLL WAN SE STRATUM 2 100TQFP |
| IDT82V3285AEQG | IC PLL WAN SE STRATUM 100TQFP |
| IDT82V3285EQG | IC PLL WAN SE STRATUM 100TQFP |
| IDT82V3288BCG | IC PLL WAN 3E STRATUM 2 208CABGA |
| IDT82V3355EDG | IC PLL WAN SYNC ETHERNET 64TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3255TFG8 | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3255TFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280APFG | 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。