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參數(shù)資料
| 型號： | IDT82V3255 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | WAN PLL |
| 中文描述： | 廣域網(wǎng)鎖相環(huán) |
| 文件頁數(shù)： | 3/127頁 |
| 文件大?。?/td> | 868K |
| 代理商： | IDT82V3255 |
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Table of Contents
3
June 19, 2006
FEATURES.............................................................................................................................................................................. 9
HIGHLIGHTS....................................................................................................................................................................................................9
MAIN FEATURES............................................................................................................................................................................................9
OTHER FEATURES.........................................................................................................................................................................................9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 11
1 PIN ASSIGNMENT ...........................................................................................................................................................12
2 PIN DESCRIPTION ..........................................................................................................................................................13
3 FUNCTIONAL DESCRIPTION .........................................................................................................................................17
3.1
RESET ...........................................................................................................................................................................................................17
3.2
MASTER CLOCK ..........................................................................................................................................................................................17
3.3
INPUT CLOCKS & FRAME SYNC SIGNALS ...............................................................................................................................................18
3.3.1
Input Clocks .................................................................................................................................................................................... 18
3.3.2
Frame SYNC Input Signals ............................................................................................................................................................ 18
3.4
INPUT CLOCK PRE-DIVIDER ......................................................................................................................................................................19
3.5
INPUT CLOCK QUALITY MONITORING .....................................................................................................................................................20
3.5.1
Activity Monitoring ......................................................................................................................................................................... 20
3.5.2
Frequency Monitoring ................................................................................................................................................................... 21
3.6
T0 / T4 DPLL INPUT CLOCK SELECTION ..................................................................................................................................................22
3.6.1
External Fast Selection (T0 only) .................................................................................................................................................. 22
3.6.2
Forced Selection ............................................................................................................................................................................ 23
3.6.3
Automatic Selection ....................................................................................................................................................................... 23
3.7
SELECTED INPUT CLOCK MONITORING ..................................................................................................................................................24
3.7.1
T0 / T4 DPLL Locking Detection ................................................................................................................................................... 24
3.7.1.1
Fast Loss .......................................................................................................................................................................... 24
3.7.1.2
Coarse Phase Loss .......................................................................................................................................................... 24
3.7.1.3
Fine Phase Loss ............................................................................................................................................................... 24
3.7.1.4
Hard Limit Exceeding ....................................................................................................................................................... 24
3.7.2
Locking Status ............................................................................................................................................................................... 24
3.7.3
Phase Lock Alarm (T0 only) .......................................................................................................................................................... 25
3.8
SELECTED INPUT CLOCK SWITCH ...........................................................................................................................................................26
3.8.1
Input Clock Validity ........................................................................................................................................................................ 26
3.8.2
Selected Input Clock Switch ......................................................................................................................................................... 26
3.8.2.1
Revertive Switch ............................................................................................................................................................... 26
3.8.2.2
Non-Revertive Switch (T0 only) ........................................................................................................................................ 27
3.8.3
Selected / Qualified Input Clocks Indication ................................................................................................................................ 27
3.9
SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE .......................................................................................................28
3.9.1
T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 28
3.9.2
T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 30
3.10 T0 / T4 DPLL OPERATING MODE ...............................................................................................................................................................31
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 31
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 31
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 31
3.10.1.3 Locked Mode .................................................................................................................................................................... 31
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 31
Table of Contents
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82V3255DK | WAN PLL |
| IDT82V3255DKG | WAN PLL |
| IDT82V3255TF | WAN PLL |
| IDT82V3255TFG | WAN PLL |
| IDT82V3280 | WAN PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3255_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DKG | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3255DKG8 | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3255EDGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
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