參數(shù)資料
型號(hào)： IDT82V2616
廠商： Integrated Device Technology, Inc.
英文描述： INVERSE MULTIPLEXING FOR ATM
中文描述： 反向復(fù)用的ATM
文件頁(yè)數(shù)： 78/375頁(yè)
文件大小： 2430K
代理商： IDT82V2616
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
67
October 7, 2003
3.19
TRANSMIT PAYLOAD CONTROL
Different test patterns can be inserted in the data stream to be
transmitted or the data stream to be transmitted can be extracted to the
PRBS Generator/Detector for test in this block.
To enable all the functions in the Transmit Payload Control, the
PCCE bit must be set to ‘1’.
The following methods can be executed on the data input from the
TSD/MTSD pins on a per-channel/per-TS basis or on a global basis (the
methods are arranged from the highest to the lowest in priority):
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
data to be transmitted will be extracted to the PRBS Generator/Detector.
The data to be transmitted can be extracted in unframed mode, in 8-bit-
based mode or in 7-bit-based mode. This selection is made by the PRB-
SMODE[1:0] bits. In unframed mode, all the data stream to be transmit-
ted is extracted and the per-channel/per-TS configuration in the TEST
bit is ignored. In 8-bit-based mode or in 7-bit-based mode, the data will
only be extracted on the channel/timeslot configured by the TEST bit.
Refer to Chapter 3.27.1 PRBS Generator / Detector for details.
- Configured by the ZCS[2:0] bits, four types of Zero Code Sup-
pression can be selected to implement to the data of all the channels.
This function is only supported in T1/J1 mode.
- Selected by the GSUBST[2:0] bits, the data of all channels/
timeslots will be replaced by the trunk code set in the DTRK[7:0] bits, the
milliwatt pattern defined in Table 38 and Table 39, or the payload loop-
back data from the Elastic Store Buffer (refer to Chapter 3.27.2.2 Pay-
load Loopback). When the GSUBST[2:0] bits are set to ‘000’, these
replacements will be performed on a per-channel/per-TS basis by set-
ting the SUBST[2:0] bits in the corresponding channel/timeslot.
- Controlled by the SIGINS bit, the signaling bits input from the
TSIG/MTSIG pins (after processed by the signaling trunk conditioning
replacement and/or valid signaling bits selection) can be inserted into its
signaling bit position of the data stream to be transmitted.
- Invert the most significant bit, the even bits and/or the odd bits by
setting the SINV, OINV, EINV bits.
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
data to be transmitted will be replaced by the test pattern generated
from the PRBS Generator/Detector. The data to be transmitted can be
replaced in unframed mode, in 8-bit-based mode or in 7-bit-based
mode. This selection is made by the PRBSMODE[1:0] bits. In unframed
mode, all the data stream to be transmitted is replaced and the per-
channel/per-TS configuration in the TEST bit is ignored. In 8-bit-based
mode or in 7-bit-based mode, the data will only be replaced on the chan-
nel/timeslot configured by the TEST bit. Refer to Chapter 3.27.1 PRBS
Generator / Detector for details.
The following methods can be executed on the signaling bits input
from the TSIG/MTSIG pins on a per-channel/per-TS basis or on a global
basis . The processed signaling bits will be inserted to the data stream to
be transmitted if frame is generated. The methods are arranged from the
highest to the lowest in priority:
- Selected by the ABXX bit, the signaling bits can be valid in the
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don’t Care
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
- Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
cuted. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
channels/timeslots will be replaced by the signaling trunk conditioning
code in the A,B,C,D bits. When the GSTRKEN bit is ‘0’, the replacement
can be performed on a per-channel/per-TS basis by setting the
STRKEN bit in the corresponding channel/timeslot.
The indirect registers of the Transmit Payload Control are accessed
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indi-
cated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
Table 45: Related Bit / Register In Chapter 3.19
Bit
Register
Address (Hex)
PCCE
TPLC Control Enable
0CC
ABXX (T1/J1 only)
TESTEN
PRBSDIR
PRBSMODE[1:0]
TEST
SIGINS (T1/J1 only)
A,B,C,D
STRKEN
ZCS[2:0] (T1/J1 only)
GSUBST[2:0]
SIGSNAP
GSTRKEN
TPLC / RPLC / PRGD Test
Configuration
0C7
ID * - Signaling Trunk Condi-
tioning Code
TPLC ID * - 41~58 (for
T1/J1) / 41~4F & 51~5F
(for E1)
TPLC Configuration
0CB
DTRK[7:0]
ID * - Data Trunk Conditioning
Code
TPLC ID * - 21~38 (for
T1/J1) / 20~3F (for E1)
SUBST[2:0]
SINV
OINV
EINV
ADDRESS[6:0]
RWN
D[7:0]
BUSY
Note:
*
ID means Indirect Register in the Transmit Payload Control function block.
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
TPLC ID * - 01~18 (for
T1/J1) / 00~1F (for E1)
TPLC Access Control
0C9
TPLC Access Data
TPLC Access Status
0CA
0C8
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