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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
25
March 5, 2009
3.8
ELASTIC STORE BUFFER (ELSB)
The Elastic Store Buffer of each framer operates independently.
3.8.1
E1 MODE
In Receive Clock Slave mode, a 2-basic-frame depth Elastic Store
Buffer is used to synchronize the incoming frames to the Receive Side
System Common Clock derived from the RSCCK pin, and to the
Receive Side System Common Frame Pulse derived from the RSCFS
pin. A write pointer is used to write the data to the Elastic Store Buffer,
while a read pointer is used to read the data from the Elastic Store
Buffer.
When the average frequency of the incoming data is greater than
that of the Receive Side System Common Clock (RSCCK), the write
pointer will be faster than the read pointer and the Elastic Store Buffer
will be filled. So a frame will be deleted after its prior frame is read.
When the read pointer crosses the frame boundary, a controlled slip will
occur with a logic 1 indicated in the SLIPD (b1, E1-059H).
When the average frequency of the incoming data is less than that
of RSCCK, the write pointer will be slower than the read pointer and the
Elastic Store Buffer will be empty. The frame will be repeated after it is
read. When the read pointer crosses the next frame boundary, a con-
trolled slip will occur with a logic 0 indicated in the SLIPD (b1, E1-059H).
When the slip occurs, the SLIPI (b0, E1-059H) will indicate. An
interrupt on the INT pin will also occur if the SLIPE (b2, E1-059H) is set
to logic 1.
In Receive Clock Slave mode, if it is out of Basic Frame synchroni-
zation, the idle code programmed in the D[7:0] (b7~0, E1-05AH) in the
Elastic Store Buffer can be set to replace the data if the TRKEN (b1, E1-
001H) is set to logic 1.
In Receive Clock Master mode, the Elastic Store Buffer is
bypassed unless the device is in the Payload Loopback diagnosis mode.
3.8.2
T1/J1 MODE
In Receive Clock Slave mode, a 2-basic-frame depth Elastic Store
Buffer is used to synchronize the incoming frames to the Receive Side
System Common Clock derived from the RSCCK pin, and to the
Receive Side System Common Frame Pulse derived from the RSCFS
pin. A write pointer is used to write the data to the Elastic Store Buffer,
while a read pointer is used to read the data from the Elastic Store
Buffer.
When the average frequency of the incoming data is greater than
that of the Receive Side System Common Clock (RSCCK), the write
pointer will be faster than the read pointer and the Elastic Store Buffer
will be filled. So a frame will be deleted after its prior frame is read.
When the read pointer crosses the frame boundary, a controlled slip will
occur with a logic 1 indicated in the SLIPD (b1, T1/J1-01DH).
When the average frequency of the incoming data is less than that
of RSCCK, the write pointer will be slower than the read pointer and the
Elastic Store Buffer will be empty. The frame will be repeated after it is
read. When the read pointer crosses the next frame boundary, a con-
trolled slip will occur with a logic 0 indicated in the SLIPD (b1, T1/J1-
01DH).
When the slip occurs, the SLIPI (b0, T1/J1-01DH) will indicate. An
interrupt on the INT pin will also occur if the SLIPE (b2, T1/J1-01DH) is
logic 1.
In Receive Clock Slave mode, if it is out of SF/ESF synchroniza-
tion, the idle code programmed in the D[7:0] (b7~0, T1/J1-01EH) in the
Elastic Store Buffer will replace the data of all channels automatically.
In Receive Clock Master mode, the Elastic Store Buffer is
bypassed unless the device is in the payload loopback diagnosis mode.